From patchwork Fri Mar 4 02:49:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: yulong@nj.iscas.ac.cn X-Patchwork-Id: 1600745 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Received: from sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4K8snp2BlNz9sGD for ; Fri, 4 Mar 2022 13:51:58 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 8E7AE3858010 for ; Fri, 4 Mar 2022 02:51:55 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from cstnet.cn (smtp84.cstnet.cn [159.226.251.84]) by sourceware.org (Postfix) with ESMTP id 24D88385803D for ; Fri, 4 Mar 2022 02:50:38 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 24D88385803D Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=nj.iscas.ac.cn Authentication-Results: sourceware.org; spf=none smtp.mailfrom=nj.iscas.ac.cn Received: from localhost.localdomain (unknown [47.88.16.30]) by APP-05 (Coremail) with SMTP id zQCowACn30FlfiFiZUgYAg--.62793S4; Fri, 04 Mar 2022 10:50:34 +0800 (CST) From: yulong@nj.iscas.ac.cn To: gcc-patches@gcc.gnu.org Subject: [PATCH 2/3] RISC-V:Cache Management Operation instructions Date: Fri, 4 Mar 2022 10:49:54 +0800 Message-Id: <20220304024955.25201-3-yulong@nj.iscas.ac.cn> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220304024955.25201-1-yulong@nj.iscas.ac.cn> References: <20220304024955.25201-1-yulong@nj.iscas.ac.cn> X-CM-TRANSID: zQCowACn30FlfiFiZUgYAg--.62793S4 X-Coremail-Antispam: 1UD129KBjvJXoWxKry5JryfKF4DGw4UWr1ftFb_yoWxKr48pa 9rGw45Cr98Zwsa9ayftFWUG34rAwnagw4Yk3srZrWqyayUX3yqyF1qka1IqrWDZF1rJr1a 93WakFy09r4jy3DanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUPC14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_Jryl82xGYIkIc2 x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2z4x0 Y4vE2Ix0cI8IcVAFwI0_Jr0_JF4l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Gr0_Cr1l84 ACjcxK6I8E87Iv67AKxVWxJVW8Jr1l84ACjcxK6I8E87Iv6xkF7I0E14v26r4UJVWxJr1l e2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E2Ix0cI 8IcVAFwI0_Jr0_Jr4lYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJVW8JwAC jcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lFIxGxcIEc7CjxVA2Y2ka0x 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cmuellner@ventanamicro.com, ptomsich@ventanamicro.com, andrew@sifive.com, sinan@isrc.iscas.ac.cn, kito.cheng@gmail.com, jiawei@iscas.ac.cn, research_trasio@irq.a4lg.com, wuwei2016@iscas.ac.cn, yulong-plct , shihua@iscas.ac.cn Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" From: yulong-plct This commit adds cbo.clea,cbo.flush,cbo.inval,cbo.zero,prefetch.i,prefetch.r and prefetch.w instructions. 7 8 gcc/ChangeLog: 9 10 * config/riscv/predicates.md (imm5_operand): Add a new operand type for prefetch instructions. 11 * config/riscv/riscv-builtins.cc (AVAIL): Add new AVAILs for CMO ISA Extensions. 12 (RISCV_ATYPE_SI): New. 13 (RISCV_ATYPE_DI): New. 14 * config/riscv/riscv-ftypes.def (0): New. 15 (1): New. 16 * config/riscv/riscv.md (riscv_clean_): Add a new mode for cbo.clean instruction. 17 (riscv_flush_): Add a new mode for cbo.flush instruction. 18 (riscv_inval_): Add a new mode for cbo.inval instruction. 19 (riscv_zero_): Add a new mode for cbo.zero instruction. 20 (prefetch): Add a new mode for prefetch.r and prefetch.w instructions. 21 (riscv_prefetchi_): Add a new mode for prefetch.i instruction. 22 * config/riscv/riscv-cmo.def: New file. --- gcc/config/riscv/predicates.md | 4 +++ gcc/config/riscv/riscv-builtins.cc | 16 +++++++++ gcc/config/riscv/riscv-cmo.def | 17 ++++++++++ gcc/config/riscv/riscv-ftypes.def | 4 +++ gcc/config/riscv/riscv.md | 52 ++++++++++++++++++++++++++++++ 5 files changed, 93 insertions(+) create mode 100644 gcc/config/riscv/riscv-cmo.def diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md index 97cdbdf053b..3fb4d95ab08 100644 --- a/gcc/config/riscv/predicates.md +++ b/gcc/config/riscv/predicates.md @@ -239,3 +239,7 @@ (define_predicate "const63_operand" (and (match_code "const_int") (match_test "INTVAL (op) == 63"))) + +(define_predicate "imm5_operand" + (and (match_code "const_int") + (match_test "INTVAL (op) < 5"))) \ No newline at end of file diff --git a/gcc/config/riscv/riscv-builtins.cc b/gcc/config/riscv/riscv-builtins.cc index 0658f8d3047..795132a0c16 100644 --- a/gcc/config/riscv/riscv-builtins.cc +++ b/gcc/config/riscv/riscv-builtins.cc @@ -87,6 +87,18 @@ struct riscv_builtin_description { AVAIL (hard_float, TARGET_HARD_FLOAT) + +AVAIL (clean32, TARGET_ZICBOM && !TARGET_64BIT) +AVAIL (clean64, TARGET_ZICBOM && TARGET_64BIT) +AVAIL (flush32, TARGET_ZICBOM && !TARGET_64BIT) +AVAIL (flush64, TARGET_ZICBOM && TARGET_64BIT) +AVAIL (inval32, TARGET_ZICBOM && !TARGET_64BIT) +AVAIL (inval64, TARGET_ZICBOM && TARGET_64BIT) +AVAIL (zero32, TARGET_ZICBOZ && !TARGET_64BIT) +AVAIL (zero64, TARGET_ZICBOZ && TARGET_64BIT) +AVAIL (prefetchi32, TARGET_ZICBOP && !TARGET_64BIT) +AVAIL (prefetchi64, TARGET_ZICBOP && TARGET_64BIT) + /* Construct a riscv_builtin_description from the given arguments. INSN is the name of the associated instruction pattern, without the @@ -119,6 +131,8 @@ AVAIL (hard_float, TARGET_HARD_FLOAT) /* Argument types. */ #define RISCV_ATYPE_VOID void_type_node #define RISCV_ATYPE_USI unsigned_intSI_type_node +#define RISCV_ATYPE_SI intSI_type_node +#define RISCV_ATYPE_DI intDI_type_node /* RISCV_FTYPE_ATYPESN takes N RISCV_FTYPES-like type codes and lists their associated RISCV_ATYPEs. */ @@ -128,6 +142,8 @@ AVAIL (hard_float, TARGET_HARD_FLOAT) RISCV_ATYPE_##A, RISCV_ATYPE_##B static const struct riscv_builtin_description riscv_builtins[] = { + #include "riscv-cmo.def" + DIRECT_BUILTIN (frflags, RISCV_USI_FTYPE, hard_float), DIRECT_NO_TARGET_BUILTIN (fsflags, RISCV_VOID_FTYPE_USI, hard_float) }; diff --git a/gcc/config/riscv/riscv-cmo.def b/gcc/config/riscv/riscv-cmo.def new file mode 100644 index 00000000000..8829a1d664d --- /dev/null +++ b/gcc/config/riscv/riscv-cmo.def @@ -0,0 +1,17 @@ +// zicbom +RISCV_BUILTIN (clean_si, "clean", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE, clean32), +RISCV_BUILTIN (clean_di, "clean", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE, clean64), + +RISCV_BUILTIN (flush_si, "flush", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE, flush32), +RISCV_BUILTIN (flush_di, "flush", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE, flush64), + +RISCV_BUILTIN (inval_si, "inval", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE, inval32), +RISCV_BUILTIN (inval_di, "inval", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE, inval64), + +// zicboz +RISCV_BUILTIN (zero_si, "zero", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE, zero32), +RISCV_BUILTIN (zero_di, "zero", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE, zero64), + +// zicbop +RISCV_BUILTIN (prefetchi_si, "prefetchi", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, prefetchi32), +RISCV_BUILTIN (prefetchi_di, "prefetchi", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI, prefetchi64), \ No newline at end of file diff --git a/gcc/config/riscv/riscv-ftypes.def b/gcc/config/riscv/riscv-ftypes.def index 2214c496f9b..62421292ce7 100644 --- a/gcc/config/riscv/riscv-ftypes.def +++ b/gcc/config/riscv/riscv-ftypes.def @@ -28,3 +28,7 @@ along with GCC; see the file COPYING3. If not see DEF_RISCV_FTYPE (0, (USI)) DEF_RISCV_FTYPE (1, (VOID, USI)) +DEF_RISCV_FTYPE (0, (SI)) +DEF_RISCV_FTYPE (0, (DI)) +DEF_RISCV_FTYPE (1, (SI, SI)) +DEF_RISCV_FTYPE (1, (DI, DI)) diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index b3c5bce842a..43ad6e5a481 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -45,6 +45,11 @@ ;; Stack tie UNSPEC_TIE + UNSPEC_CLEAN + UNSPEC_FLUSH + UNSPEC_INVAL + UNSPEC_ZERO + UNSPEC_PREI ]) (define_c_enum "unspecv" [ @@ -69,6 +74,7 @@ ;; Stack Smash Protector UNSPEC_SSP_SET UNSPEC_SSP_TEST + ]) (define_constants @@ -2863,6 +2869,52 @@ "\t%3, %1\;\t%0, %2\;xor\t%0, %3, %0\;li\t%3, 0" [(set_attr "length" "12")]) +(define_insn "riscv_clean_" +[(unspec:X [(match_operand:X 0 "register_operand" "r")] UNSPEC_CLEAN)] +"TARGET_ZICBOM" +"cbo.clean\t%0" +) + +(define_insn "riscv_flush_" +[(unspec:X [(match_operand:X 0 "register_operand" "r")] UNSPEC_FLUSH)] +"TARGET_ZICBOM" +"cbo.flush\t%0" +) + +(define_insn "riscv_inval_" +[(unspec:X [(match_operand:X 0 "register_operand" "r")] UNSPEC_INVAL)] +"TARGET_ZICBOM" +"cbo.inval\t%0" +) + +(define_insn "riscv_zero_" +[(unspec:X [(match_operand:X 0 "register_operand" "r")] UNSPEC_ZERO)] +"TARGET_ZICBOZ" +"cbo.zero\t%0" +) + +(define_insn "prefetch" +[(prefetch (match_operand 0 "address_operand" "p") + (match_operand 1 "imm5_operand" "i") + (match_operand 2 "const_int_operand" "n"))] +"TARGET_ZICBOP" +{ + switch (INTVAL (operands[1])) + { + case 0: return "prefetch.r\t%a0"; + case 1: return "prefetch.w\t%a0"; + default: gcc_unreachable (); + } +}) + +(define_insn "riscv_prefetchi_" +[(unspec:X [(match_operand:X 0 "address_operand" "p") + (match_operand:X 1 "imm5_operand" "i")] + UNSPEC_PREI)] +"TARGET_ZICBOP" +"prefetch.i\t%0" +) + (include "bitmanip.md") (include "sync.md") (include "peephole.md")