Message ID | 20220106092102.32982-1-hongtao.liu@intel.com |
---|---|
State | New |
Headers | show |
Series | [i386] Optimize V16HF vector insert to element 0 for AVX2. | expand |
On Thu, Jan 6, 2022 at 10:22 AM liuhongt via Gcc-patches <gcc-patches@gcc.gnu.org> wrote: > > Also remove mode attribute blendsuf, use ssemodesuf instead. > Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}. > Ready to push to trunk. > > gcc/ChangeLog: > > PR target/103753 > * config/i386/i386-expand.c (ix86_expand_vector_set): Not use > gen_avx2_pblendph_pblendd when elt == 0. > * config/i386/sse.md (avx2_pblendph): Rename to .. > (avx2_pblend<ssemodesuffix>_pblendd).. this, and extend to V16HI. > (*avx2_pblendw): Rename to .. > (*avx2_pblend<ssemodesuffix>): .. this, and extend to V16HF. > (avx2_pblendw): Rename to .. > (*avx2_pblend<ssemodesuffix>): .. this, and extend to V16HF. > (blendsuf): Removed. > (sse4_1_pblend<blendsuf>): Renamed to .. > (sse4_1_pblend<ssemodesuffix>): .. this. > > gcc/testsuite/ChangeLog: > > * gcc.target/i386/pr103753.c: New test. LGTM, with a small nit below. Thanks, Uros. > --- > gcc/config/i386/i386-expand.c | 5 ++- > gcc/config/i386/sse.md | 48 +++++++++++------------- > gcc/testsuite/gcc.target/i386/pr103753.c | 17 +++++++++ > 3 files changed, 42 insertions(+), 28 deletions(-) > create mode 100644 gcc/testsuite/gcc.target/i386/pr103753.c > > diff --git a/gcc/config/i386/i386-expand.c b/gcc/config/i386/i386-expand.c > index e93ef1cafa6..0d219d6bb69 100644 > --- a/gcc/config/i386/i386-expand.c > +++ b/gcc/config/i386/i386-expand.c > @@ -16245,10 +16245,11 @@ ix86_expand_vector_set (bool mmx_ok, rtx target, rtx val, int elt) > goto half; > > case E_V16HFmode: > - if (TARGET_AVX2) > + /* For ELT == 0, vec_setv8hf_0 can save 1 vpbroadcastw. */ > + if (TARGET_AVX2 && elt != 0) > { > mmode = SImode; > - gen_blendm = gen_avx2_pblendph; > + gen_blendm = gen_avx2_pblendph_pblendd; > blendm_const = true; > break; > } > diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md > index 033b60d9aa2..c986c73bef8 100644 > --- a/gcc/config/i386/sse.md > +++ b/gcc/config/i386/sse.md > @@ -21291,10 +21291,7 @@ (define_insn_and_split "*<sse4_1_avx2>_pblendvb_lt_subreg_not" > (lt:VI1_AVX2 (match_dup 3) (match_dup 4))] UNSPEC_BLENDV))] > "operands[3] = gen_lowpart (<MODE>mode, operands[3]);") > > -(define_mode_attr blendsuf > - [(V8HI "w") (V8HF "ph")]) > - > -(define_insn "sse4_1_pblend<blendsuf>" > +(define_insn "sse4_1_pblend<ssemodesuffix>" > [(set (match_operand:V8_128 0 "register_operand" "=Yr,*x,x") > (vec_merge:V8_128 > (match_operand:V8_128 2 "vector_operand" "YrBm,*xBm,xm") > @@ -21313,11 +21310,11 @@ (define_insn "sse4_1_pblend<blendsuf>" > (set_attr "mode" "TI")]) > > ;; The builtin uses an 8-bit immediate. Expand that. > -(define_expand "avx2_pblendw" > - [(set (match_operand:V16HI 0 "register_operand") > - (vec_merge:V16HI > - (match_operand:V16HI 2 "nonimmediate_operand") > - (match_operand:V16HI 1 "register_operand") > +(define_expand "avx2_pblend<ssemodesuffix>" > + [(set (match_operand:V16_256 0 "register_operand") > + (vec_merge:V16_256 > + (match_operand:V16_256 2 "nonimmediate_operand") > + (match_operand:V16_256 1 "register_operand") > (match_operand:SI 3 "const_0_to_255_operand")))] > "TARGET_AVX2" > { > @@ -21325,11 +21322,11 @@ (define_expand "avx2_pblendw" > operands[3] = GEN_INT (val << 8 | val); > }) > > -(define_expand "avx2_pblendph" > - [(set (match_operand:V16HF 0 "register_operand") > - (vec_merge:V16HF > - (match_operand:V16HF 2 "register_operand") > - (match_operand:V16HF 1 "register_operand") > +(define_expand "avx2_pblend<ssemodesuffix>_pblendd" Just name the above avx2_pblend<ssemodesuffix>_1. > + [(set (match_operand:V16_256 0 "register_operand") > + (vec_merge:V16_256 > + (match_operand:V16_256 2 "register_operand") > + (match_operand:V16_256 1 "register_operand") > (match_operand:SI 3 "const_int_operand")))] > "TARGET_AVX2 > && !((INTVAL (operands[3]) & 0xff) && (INTVAL (operands[3]) & 0xff00))" > @@ -21339,7 +21336,7 @@ (define_expand "avx2_pblendph" > emit_move_insn (operands[0], operands[1]); > else > { > - rtx tmp = gen_reg_rtx (V16HImode); > + rtx tmp = gen_reg_rtx (<MODE>mode); > rtx blendw_idx, blendd_idx; > > if (mask & 0xff) > @@ -21352,13 +21349,12 @@ (define_expand "avx2_pblendph" > blendw_idx = GEN_INT (mask >> 8 & 0xff); > blendd_idx = GEN_INT (240); > } > - operands[1] = lowpart_subreg (V16HImode, operands[1], V16HFmode); > - operands[2] = lowpart_subreg (V16HImode, operands[2], V16HFmode); > - emit_insn (gen_avx2_pblendw (tmp, operands[1], operands[2], blendw_idx)); > + emit_insn (gen_avx2_pblend<ssemodesuffix> (tmp, operands[1], > + operands[2], blendw_idx)); > > - operands[0] = lowpart_subreg (V8SImode, operands[0], V16HFmode); > - tmp = lowpart_subreg (V8SImode, tmp, V16HImode); > - operands[1] = lowpart_subreg (V8SImode, operands[1], V16HImode); > + operands[0] = lowpart_subreg (V8SImode, operands[0], <MODE>mode); > + tmp = lowpart_subreg (V8SImode, tmp, <MODE>mode); > + operands[1] = lowpart_subreg (V8SImode, operands[1], <MODE>mode); > emit_insn (gen_avx2_pblenddv8si (operands[0], operands[1], > tmp, blendd_idx)); > } > @@ -21366,11 +21362,11 @@ (define_expand "avx2_pblendph" > DONE; > }) > > -(define_insn "*avx2_pblendw" > - [(set (match_operand:V16HI 0 "register_operand" "=x") > - (vec_merge:V16HI > - (match_operand:V16HI 2 "nonimmediate_operand" "xm") > - (match_operand:V16HI 1 "register_operand" "x") > +(define_insn "*avx2_pblend<ssemodesuffix>" > + [(set (match_operand:V16_256 0 "register_operand" "=x") > + (vec_merge:V16_256 > + (match_operand:V16_256 2 "nonimmediate_operand" "xm") > + (match_operand:V16_256 1 "register_operand" "x") > (match_operand:SI 3 "avx2_pblendw_operand" "n")))] > "TARGET_AVX2" > { > diff --git a/gcc/testsuite/gcc.target/i386/pr103753.c b/gcc/testsuite/gcc.target/i386/pr103753.c > new file mode 100644 > index 00000000000..4b2b3e46d8b > --- /dev/null > +++ b/gcc/testsuite/gcc.target/i386/pr103753.c > @@ -0,0 +1,17 @@ > +/* { dg-do compile } */ > +/* { dg-options "-mavx2 -mno-avx512f -O2" } */ > +/* { dg-final { scan-assembler-not "vpbroadcastw" } } */ > + > +typedef _Float16 __v16hf __attribute__ ((__vector_size__ (32))); > + > +__v16hf foo (_Float16 x) > +{ > + return (__v16hf) { x, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f }; > +} > + > +typedef short __v16hi __attribute__ ((__vector_size__ (32))); > + > +__v16hi bar (short x) > +{ > + return (__v16hi) { x, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; > +} > -- > 2.18.1 >
diff --git a/gcc/config/i386/i386-expand.c b/gcc/config/i386/i386-expand.c index e93ef1cafa6..0d219d6bb69 100644 --- a/gcc/config/i386/i386-expand.c +++ b/gcc/config/i386/i386-expand.c @@ -16245,10 +16245,11 @@ ix86_expand_vector_set (bool mmx_ok, rtx target, rtx val, int elt) goto half; case E_V16HFmode: - if (TARGET_AVX2) + /* For ELT == 0, vec_setv8hf_0 can save 1 vpbroadcastw. */ + if (TARGET_AVX2 && elt != 0) { mmode = SImode; - gen_blendm = gen_avx2_pblendph; + gen_blendm = gen_avx2_pblendph_pblendd; blendm_const = true; break; } diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 033b60d9aa2..c986c73bef8 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -21291,10 +21291,7 @@ (define_insn_and_split "*<sse4_1_avx2>_pblendvb_lt_subreg_not" (lt:VI1_AVX2 (match_dup 3) (match_dup 4))] UNSPEC_BLENDV))] "operands[3] = gen_lowpart (<MODE>mode, operands[3]);") -(define_mode_attr blendsuf - [(V8HI "w") (V8HF "ph")]) - -(define_insn "sse4_1_pblend<blendsuf>" +(define_insn "sse4_1_pblend<ssemodesuffix>" [(set (match_operand:V8_128 0 "register_operand" "=Yr,*x,x") (vec_merge:V8_128 (match_operand:V8_128 2 "vector_operand" "YrBm,*xBm,xm") @@ -21313,11 +21310,11 @@ (define_insn "sse4_1_pblend<blendsuf>" (set_attr "mode" "TI")]) ;; The builtin uses an 8-bit immediate. Expand that. -(define_expand "avx2_pblendw" - [(set (match_operand:V16HI 0 "register_operand") - (vec_merge:V16HI - (match_operand:V16HI 2 "nonimmediate_operand") - (match_operand:V16HI 1 "register_operand") +(define_expand "avx2_pblend<ssemodesuffix>" + [(set (match_operand:V16_256 0 "register_operand") + (vec_merge:V16_256 + (match_operand:V16_256 2 "nonimmediate_operand") + (match_operand:V16_256 1 "register_operand") (match_operand:SI 3 "const_0_to_255_operand")))] "TARGET_AVX2" { @@ -21325,11 +21322,11 @@ (define_expand "avx2_pblendw" operands[3] = GEN_INT (val << 8 | val); }) -(define_expand "avx2_pblendph" - [(set (match_operand:V16HF 0 "register_operand") - (vec_merge:V16HF - (match_operand:V16HF 2 "register_operand") - (match_operand:V16HF 1 "register_operand") +(define_expand "avx2_pblend<ssemodesuffix>_pblendd" + [(set (match_operand:V16_256 0 "register_operand") + (vec_merge:V16_256 + (match_operand:V16_256 2 "register_operand") + (match_operand:V16_256 1 "register_operand") (match_operand:SI 3 "const_int_operand")))] "TARGET_AVX2 && !((INTVAL (operands[3]) & 0xff) && (INTVAL (operands[3]) & 0xff00))" @@ -21339,7 +21336,7 @@ (define_expand "avx2_pblendph" emit_move_insn (operands[0], operands[1]); else { - rtx tmp = gen_reg_rtx (V16HImode); + rtx tmp = gen_reg_rtx (<MODE>mode); rtx blendw_idx, blendd_idx; if (mask & 0xff) @@ -21352,13 +21349,12 @@ (define_expand "avx2_pblendph" blendw_idx = GEN_INT (mask >> 8 & 0xff); blendd_idx = GEN_INT (240); } - operands[1] = lowpart_subreg (V16HImode, operands[1], V16HFmode); - operands[2] = lowpart_subreg (V16HImode, operands[2], V16HFmode); - emit_insn (gen_avx2_pblendw (tmp, operands[1], operands[2], blendw_idx)); + emit_insn (gen_avx2_pblend<ssemodesuffix> (tmp, operands[1], + operands[2], blendw_idx)); - operands[0] = lowpart_subreg (V8SImode, operands[0], V16HFmode); - tmp = lowpart_subreg (V8SImode, tmp, V16HImode); - operands[1] = lowpart_subreg (V8SImode, operands[1], V16HImode); + operands[0] = lowpart_subreg (V8SImode, operands[0], <MODE>mode); + tmp = lowpart_subreg (V8SImode, tmp, <MODE>mode); + operands[1] = lowpart_subreg (V8SImode, operands[1], <MODE>mode); emit_insn (gen_avx2_pblenddv8si (operands[0], operands[1], tmp, blendd_idx)); } @@ -21366,11 +21362,11 @@ (define_expand "avx2_pblendph" DONE; }) -(define_insn "*avx2_pblendw" - [(set (match_operand:V16HI 0 "register_operand" "=x") - (vec_merge:V16HI - (match_operand:V16HI 2 "nonimmediate_operand" "xm") - (match_operand:V16HI 1 "register_operand" "x") +(define_insn "*avx2_pblend<ssemodesuffix>" + [(set (match_operand:V16_256 0 "register_operand" "=x") + (vec_merge:V16_256 + (match_operand:V16_256 2 "nonimmediate_operand" "xm") + (match_operand:V16_256 1 "register_operand" "x") (match_operand:SI 3 "avx2_pblendw_operand" "n")))] "TARGET_AVX2" { diff --git a/gcc/testsuite/gcc.target/i386/pr103753.c b/gcc/testsuite/gcc.target/i386/pr103753.c new file mode 100644 index 00000000000..4b2b3e46d8b --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr103753.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -mno-avx512f -O2" } */ +/* { dg-final { scan-assembler-not "vpbroadcastw" } } */ + +typedef _Float16 __v16hf __attribute__ ((__vector_size__ (32))); + +__v16hf foo (_Float16 x) +{ + return (__v16hf) { x, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f }; +} + +typedef short __v16hi __attribute__ ((__vector_size__ (32))); + +__v16hi bar (short x) +{ + return (__v16hi) { x, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; +}