| Message ID | 20220104052005.381-1-lili.cui@intel.com |
|---|---|
| State | New |
| Headers | show |
| Series | x86: Update model value for Alderlake and Rocketlake | expand |
> -----Original Message----- > From: Cui, Lili <lili.cui@intel.com> > Sent: Tuesday, January 4, 2022 1:20 PM > To: gcc-patches@gcc.gnu.org > Cc: ubizjak@gmail.com; Liu, Hongtao <hongtao.liu@intel.com>; > hjl.tools@gmail.com > Subject: [PATCH] x86: Update model value for Alderlake and Rocketlake > > Hi Uros, > > This patch is to update model value for Alderlake and Rocketlake. Just note the update is according to latest https://www.intel.com/content/dam/develop/public/us/en/documents/325462-sdm-vol-1-2abcd-3abcd.pdf > > Bootstrap is ok, and no regressions for i386/x86-64 testsuite. > > OK for master? > > gcc/ChangeLog > > * common/config/i386/cpuinfo.h (get_intel_cpu): Add new model > values > to Alderlake and Rocketlake. > --- > gcc/common/config/i386/cpuinfo.h | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/gcc/common/config/i386/cpuinfo.h > b/gcc/common/config/i386/cpuinfo.h > index 2d8ea201ab5..61b1a0f291c 100644 > --- a/gcc/common/config/i386/cpuinfo.h > +++ b/gcc/common/config/i386/cpuinfo.h > @@ -415,6 +415,7 @@ get_intel_cpu (struct __processor_model > *cpu_model, > cpu_model->__cpu_subtype = INTEL_COREI7_SKYLAKE; > break; > case 0xa7: > + case 0xa8: > /* Rocket Lake. */ > cpu = "rocketlake"; > CHECK___builtin_cpu_is ("corei7"); @@ -487,6 +488,7 @@ get_intel_cpu > (struct __processor_model *cpu_model, > break; > case 0x97: > case 0x9a: > + case 0xbf: > /* Alder Lake. */ > cpu = "alderlake"; > CHECK___builtin_cpu_is ("corei7"); > -- > 2.17.1 > > Thanks, > Lili.
On Tue, Jan 4, 2022 at 6:20 AM Cui,Lili <lili.cui@intel.com> wrote: > > Hi Uros, > > This patch is to update model value for Alderlake and Rocketlake. > > Bootstrap is ok, and no regressions for i386/x86-64 testsuite. > > OK for master? > > gcc/ChangeLog > > * common/config/i386/cpuinfo.h (get_intel_cpu): Add new model values > to Alderlake and Rocketlake. OK (this patch can be considered as an obvious patch). Thanks, Uros. > --- > gcc/common/config/i386/cpuinfo.h | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/gcc/common/config/i386/cpuinfo.h b/gcc/common/config/i386/cpuinfo.h > index 2d8ea201ab5..61b1a0f291c 100644 > --- a/gcc/common/config/i386/cpuinfo.h > +++ b/gcc/common/config/i386/cpuinfo.h > @@ -415,6 +415,7 @@ get_intel_cpu (struct __processor_model *cpu_model, > cpu_model->__cpu_subtype = INTEL_COREI7_SKYLAKE; > break; > case 0xa7: > + case 0xa8: > /* Rocket Lake. */ > cpu = "rocketlake"; > CHECK___builtin_cpu_is ("corei7"); > @@ -487,6 +488,7 @@ get_intel_cpu (struct __processor_model *cpu_model, > break; > case 0x97: > case 0x9a: > + case 0xbf: > /* Alder Lake. */ > cpu = "alderlake"; > CHECK___builtin_cpu_is ("corei7"); > -- > 2.17.1 > > Thanks, > Lili.
diff --git a/gcc/common/config/i386/cpuinfo.h b/gcc/common/config/i386/cpuinfo.h index 2d8ea201ab5..61b1a0f291c 100644 --- a/gcc/common/config/i386/cpuinfo.h +++ b/gcc/common/config/i386/cpuinfo.h @@ -415,6 +415,7 @@ get_intel_cpu (struct __processor_model *cpu_model, cpu_model->__cpu_subtype = INTEL_COREI7_SKYLAKE; break; case 0xa7: + case 0xa8: /* Rocket Lake. */ cpu = "rocketlake"; CHECK___builtin_cpu_is ("corei7"); @@ -487,6 +488,7 @@ get_intel_cpu (struct __processor_model *cpu_model, break; case 0x97: case 0x9a: + case 0xbf: /* Alder Lake. */ cpu = "alderlake"; CHECK___builtin_cpu_is ("corei7");