Message ID | 20211229012740.3245971-1-luoxhu@linux.ibm.com |
---|---|
State | New |
Headers | show |
Series | rs6000: Add split pattern to replace | expand |
Gentle ping, thanks. On 2021/12/29 09:27, Xionghu Luo wrote: > 7: r120:V4SI=const_vector > 8: r121:V4SI=unspec[r120:V4SI,r120:V4SI,0xc] 260 > > with r121:v4SI = r120:V4SI when r120 is a vector with same element. > > Bootstrapped and regtested pass on powerpc64le-linux-gnu {P10, P9} > and powerpc64-linux-gnu {P8, P7}. OK for master? > > gcc/ChangeLog: > > * config/rs6000/altivec.md (sldoi_to_mov_<mode>): New. > > gcc/testsuite/ChangeLog: > > * gcc.target/powerpc/sldoi_to_mov.c: New test. > --- > gcc/config/rs6000/altivec.md | 11 +++++++++++ > gcc/testsuite/gcc.target/powerpc/sldoi_to_mov.c | 15 +++++++++++++++ > 2 files changed, 26 insertions(+) > create mode 100644 gcc/testsuite/gcc.target/powerpc/sldoi_to_mov.c > > diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md > index b2909857c34..25f86dbe828 100644 > --- a/gcc/config/rs6000/altivec.md > +++ b/gcc/config/rs6000/altivec.md > @@ -383,6 +383,17 @@ (define_split > } > }) > > +(define_insn_and_split "sldoi_to_mov_<mode>" > + [(set (match_operand:VM 0 "altivec_register_operand") > + (unspec:VM [(match_operand:VM 1 "easy_vector_constant") > + (match_dup 1) > + (match_operand:VM 2 "u5bit_cint_operand")] > + UNSPEC_VSLDOI))] > + "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode) && can_create_pseudo_p ()" > + "#" > + "&& 1" > + [(set (match_dup 0) (match_dup 1))]) > + > (define_insn "get_vrsave_internal" > [(set (match_operand:SI 0 "register_operand" "=r") > (unspec:SI [(reg:SI VRSAVE_REGNO)] UNSPEC_GET_VRSAVE))] > diff --git a/gcc/testsuite/gcc.target/powerpc/sldoi_to_mov.c b/gcc/testsuite/gcc.target/powerpc/sldoi_to_mov.c > new file mode 100644 > index 00000000000..2053243c456 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/powerpc/sldoi_to_mov.c > @@ -0,0 +1,15 @@ > +/* { dg-do compile } */ > +/* { dg-options "-O2" } */ > + > +#include <altivec.h> > +vector signed int foo1 (vector signed int a) { > + vector signed int b = {0}; > + return vec_sum2s(a, b); > +} > + > +vector signed int foo2 (vector signed int a) { > + vector signed int b = {0}; > + return vec_sld(b, b, 4); > +} > + > +/* { dg-final { scan-assembler-times {\mvsldoi\M} 1 {target le} } } */
On Mon, Jan 10, 2022 at 12:04 AM Xionghu Luo <luoxhu@linux.ibm.com> wrote: > > Gentle ping, thanks. > > > On 2021/12/29 09:27, Xionghu Luo wrote: > > 7: r120:V4SI=const_vector > > 8: r121:V4SI=unspec[r120:V4SI,r120:V4SI,0xc] 260 > > > > with r121:v4SI = r120:V4SI when r120 is a vector with same element. > > > > Bootstrapped and regtested pass on powerpc64le-linux-gnu {P10, P9} > > and powerpc64-linux-gnu {P8, P7}. OK for master? > > > > gcc/ChangeLog: > > > > * config/rs6000/altivec.md (sldoi_to_mov_<mode>): New. > > > > gcc/testsuite/ChangeLog: > > > > * gcc.target/powerpc/sldoi_to_mov.c: New test. > > --- > > gcc/config/rs6000/altivec.md | 11 +++++++++++ > > gcc/testsuite/gcc.target/powerpc/sldoi_to_mov.c | 15 +++++++++++++++ > > 2 files changed, 26 insertions(+) > > create mode 100644 gcc/testsuite/gcc.target/powerpc/sldoi_to_mov.c > > > > diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md > > index b2909857c34..25f86dbe828 100644 > > --- a/gcc/config/rs6000/altivec.md > > +++ b/gcc/config/rs6000/altivec.md > > @@ -383,6 +383,17 @@ (define_split > > } > > }) > > > > +(define_insn_and_split "sldoi_to_mov_<mode>" It would be more consistent with the naming convention to use "sldoi_to_mov<mode>" without the final "_". > > + [(set (match_operand:VM 0 "altivec_register_operand") > > + (unspec:VM [(match_operand:VM 1 "easy_vector_constant") Should this be "easy_vector_constant_vsldoi"? > > + (match_dup 1) > > + (match_operand:VM 2 "u5bit_cint_operand")] This should be match_operand:QI, right? Thanks, David > > + UNSPEC_VSLDOI))] > > + "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode) && can_create_pseudo_p ()" > > + "#" > > + "&& 1" > > + [(set (match_dup 0) (match_dup 1))]) > > + > > (define_insn "get_vrsave_internal" > > [(set (match_operand:SI 0 "register_operand" "=r") > > (unspec:SI [(reg:SI VRSAVE_REGNO)] UNSPEC_GET_VRSAVE))] > > diff --git a/gcc/testsuite/gcc.target/powerpc/sldoi_to_mov.c b/gcc/testsuite/gcc.target/powerpc/sldoi_to_mov.c > > new file mode 100644 > > index 00000000000..2053243c456 > > --- /dev/null > > +++ b/gcc/testsuite/gcc.target/powerpc/sldoi_to_mov.c > > @@ -0,0 +1,15 @@ > > +/* { dg-do compile } */ > > +/* { dg-options "-O2" } */ > > + > > +#include <altivec.h> > > +vector signed int foo1 (vector signed int a) { > > + vector signed int b = {0}; > > + return vec_sum2s(a, b); > > +} > > + > > +vector signed int foo2 (vector signed int a) { > > + vector signed int b = {0}; > > + return vec_sld(b, b, 4); > > +} > > + > > +/* { dg-final { scan-assembler-times {\mvsldoi\M} 1 {target le} } } */ > > -- > Thanks, > Xionghu
On 2022/1/11 06:55, David Edelsohn wrote: >>> +(define_insn_and_split "sldoi_to_mov_<mode>" > It would be more consistent with the naming convention to use > "sldoi_to_mov<mode>" without the final "_". OK, thanks. > >>> + [(set (match_operand:VM 0 "altivec_register_operand") >>> + (unspec:VM [(match_operand:VM 1 "easy_vector_constant") > Should this be "easy_vector_constant_vsldoi"? This doesn't work. easy_vector_constant_vsldoi return false due to vspltis_shifted "return 0" as: vspltis_shifted (rtx op): /* If all elements are equal, we don't need to do VSLDOI. */ (gdb) p op $7 = (rtx_def *) (const_vector:V4SI [ (const_int 0 [0]) repeated x4 ]) (gdb) p easy_vector_constant_vsldoi(op, V4SImode) $8 = false p easy_vector_constant(op, V4SImode) $9 = true > >>> + (match_dup 1) >>> + (match_operand:VM 2 "u5bit_cint_operand")] > This should be match_operand:QI, right? Yes. > > Thanks, David >
On Tue, Jan 11, 2022 at 2:27 AM Xionghu Luo <luoxhu@linux.ibm.com> wrote: > > On 2022/1/11 06:55, David Edelsohn wrote: > >>> +(define_insn_and_split "sldoi_to_mov_<mode>" > > It would be more consistent with the naming convention to use > > "sldoi_to_mov<mode>" without the final "_". > > OK, thanks. > > > > >>> + [(set (match_operand:VM 0 "altivec_register_operand") > >>> + (unspec:VM [(match_operand:VM 1 "easy_vector_constant") > > Should this be "easy_vector_constant_vsldoi"? > > > This doesn't work. easy_vector_constant_vsldoi return false due to > vspltis_shifted "return 0" as: > > vspltis_shifted (rtx op): /* If all elements are equal, we don't need to do VSLDOI. */ > > > (gdb) p op > $7 = (rtx_def *) (const_vector:V4SI [ > (const_int 0 [0]) repeated x4 > ]) > (gdb) p easy_vector_constant_vsldoi(op, V4SImode) > $8 = false > p easy_vector_constant(op, V4SImode) > $9 = true Okay, thanks for checking. > > > > >>> + (match_dup 1) > >>> + (match_operand:VM 2 "u5bit_cint_operand")] > > This should be match_operand:QI, right? > > Yes. This patch is okay with the other changes. Thanks, David
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md index b2909857c34..25f86dbe828 100644 --- a/gcc/config/rs6000/altivec.md +++ b/gcc/config/rs6000/altivec.md @@ -383,6 +383,17 @@ (define_split } }) +(define_insn_and_split "sldoi_to_mov_<mode>" + [(set (match_operand:VM 0 "altivec_register_operand") + (unspec:VM [(match_operand:VM 1 "easy_vector_constant") + (match_dup 1) + (match_operand:VM 2 "u5bit_cint_operand")] + UNSPEC_VSLDOI))] + "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode) && can_create_pseudo_p ()" + "#" + "&& 1" + [(set (match_dup 0) (match_dup 1))]) + (define_insn "get_vrsave_internal" [(set (match_operand:SI 0 "register_operand" "=r") (unspec:SI [(reg:SI VRSAVE_REGNO)] UNSPEC_GET_VRSAVE))] diff --git a/gcc/testsuite/gcc.target/powerpc/sldoi_to_mov.c b/gcc/testsuite/gcc.target/powerpc/sldoi_to_mov.c new file mode 100644 index 00000000000..2053243c456 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/sldoi_to_mov.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +#include <altivec.h> +vector signed int foo1 (vector signed int a) { + vector signed int b = {0}; + return vec_sum2s(a, b); +} + +vector signed int foo2 (vector signed int a) { + vector signed int b = {0}; + return vec_sld(b, b, 4); +} + +/* { dg-final { scan-assembler-times {\mvsldoi\M} 1 {target le} } } */