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([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id a23sm274427ljh.140.2021.11.11.06.10.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Nov 2021 06:10:26 -0800 (PST) From: Philipp Tomsich To: gcc-patches@gcc.gnu.org Subject: [PATCH v1 4/8] RISC-V: bitmanip: fix constant-loading for (1ULL << 31) in DImode Date: Thu, 11 Nov 2021 15:10:16 +0100 Message-Id: <20211111141020.2738001-5-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211111141020.2738001-1-philipp.tomsich@vrull.eu> References: <20211111141020.2738001-1-philipp.tomsich@vrull.eu> MIME-Version: 1.0 X-Spam-Status: No, score=-12.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: wilson@tuliptree.org, kito.cheng@gmail.com, Philipp Tomsich Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" The SINGLE_BIT_MASK_OPERAND() is overly restrictive, triggering for bits above 31 only (to side-step any issues with the negative SImode value 0x80000000). This moves the special handling of this SImode value (i.e. the check for -2147483648) to riscv.c and relaxes the SINGLE_BIT_MASK_OPERAND() test. This changes the code-generation for loading (1ULL << 31) from: li a0,1 slli a0,a0,31 to: bseti a0,zero,31 gcc/ChangeLog: * config/riscv/riscv.c (riscv_build_integer_1): Rewrite value as -2147483648 for the single-bit case, when operating on 0x80000000 in SImode. * gcc/config/riscv/riscv.h (SINGLE_BIT_MASK_OPERAND): Allow for any single-bit value, moving the special case for 0x80000000 to riscv_build_integer_1 (in riscv.c). Signed-off-by: Philipp Tomsich --- gcc/config/riscv/riscv.c | 9 +++++++++ gcc/config/riscv/riscv.h | 11 ++++------- 2 files changed, 13 insertions(+), 7 deletions(-) diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c index dff4e370471..4c30d4e521d 100644 --- a/gcc/config/riscv/riscv.c +++ b/gcc/config/riscv/riscv.c @@ -415,6 +415,15 @@ riscv_build_integer_1 (struct riscv_integer_op codes[RISCV_MAX_INTEGER_OPS], /* Simply BSETI. */ codes[0].code = UNKNOWN; codes[0].value = value; + + /* RISC-V sign-extends all 32bit values that life in a 32bit + register. To avoid paradoxes, we thus need to use the + sign-extended (negative) representation for the value, if we + want to build 0x80000000 in SImode. This will then expand + to an ADDI/LI instruction. */ + if (mode == SImode && value == 0x80000000) + codes[0].value = -2147483648; + return 1; } diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h index 64287124735..abb121ddbea 100644 --- a/gcc/config/riscv/riscv.h +++ b/gcc/config/riscv/riscv.h @@ -526,13 +526,10 @@ enum reg_class (((VALUE) | ((1UL<<31) - IMM_REACH)) == ((1UL<<31) - IMM_REACH) \ || ((VALUE) | ((1UL<<31) - IMM_REACH)) + IMM_REACH == 0) -/* If this is a single bit mask, then we can load it with bseti. But this - is not useful for any of the low 31 bits because we can use addi or lui - to load them. It is wrong for loading SImode 0x80000000 on rv64 because it - needs to be sign-extended. So we restrict this to the upper 32-bits - only. */ -#define SINGLE_BIT_MASK_OPERAND(VALUE) \ - (pow2p_hwi (VALUE) && (ctz_hwi (VALUE) >= 32)) +/* If this is a single bit mask, then we can load it with bseti. Special + handling of SImode 0x80000000 on RV64 is done in riscv_build_integer_1. */ +#define SINGLE_BIT_MASK_OPERAND(VALUE) \ + (pow2p_hwi (VALUE)) /* Stack layout; function entry, exit and calling. */