| Message ID | 20210929162024.GA1924@arm.com |
|---|---|
| State | New |
| Headers | show |
| Series | AArch64 Optimize truncation, shifts and bitmask comparisons | expand |
> -----Original Message----- > From: Tamar Christina <Tamar.Christina@arm.com> > Sent: Wednesday, September 29, 2021 5:20 PM > To: gcc-patches@gcc.gnu.org > Cc: nd <nd@arm.com>; Richard Earnshaw <Richard.Earnshaw@arm.com>; > Marcus Shawcroft <Marcus.Shawcroft@arm.com>; Kyrylo Tkachov > <Kyrylo.Tkachov@arm.com>; Richard Sandiford > <Richard.Sandiford@arm.com> > Subject: [PATCH 4/7]AArch64 Add pattern xtn+xtn2 to uzp2 > > Hi All, > > This turns truncate operations with a hi/lo pair into a single permute of half > the bit size of the input and just ignoring the top bits (which are truncated > out). > > i.e. > > void d2 (short * restrict a, int *b, int n) > { > for (int i = 0; i < n; i++) > a[i] = b[i]; > } > > now generates: > > .L4: > ldp q0, q1, [x3] > add x3, x3, 32 > uzp1 v0.8h, v0.8h, v1.8h > str q0, [x5], 16 > cmp x4, x3 > bne .L4 > > instead of > > .L4: > ldp q0, q1, [x3] > add x3, x3, 32 > xtn v0.4h, v0.4s > xtn2 v0.8h, v1.4s > str q0, [x5], 16 > cmp x4, x3 > bne .L4 > > Bootstrapped Regtested on aarch64-none-linux-gnu and no issues. > > Ok for master? > Ok. Thanks, Kyrill > Thanks, > Tamar > > gcc/ChangeLog: > > * config/aarch64/aarch64-simd.md > (*aarch64_narrow_trunc<mode>): New. > * config/aarch64/iterators.md (VNARROWSIMD, Vnarrowsimd): > New. > > gcc/testsuite/ChangeLog: > > * gcc.target/aarch64/xtn-combine-1.c: New test. > * gcc.target/aarch64/narrow_high_combine.c: Update case. > > --- inline copy of patch -- > diff --git a/gcc/config/aarch64/aarch64-simd.md > b/gcc/config/aarch64/aarch64-simd.md > index > 36396ef236e8c476d5e2f1acee80dc54ec5ebe4e..33e3301d229366022a5b9481 > b6c3ae8f8d93f9e2 100644 > --- a/gcc/config/aarch64/aarch64-simd.md > +++ b/gcc/config/aarch64/aarch64-simd.md > @@ -1753,6 +1753,18 @@ (define_expand "aarch64_xtn2<mode>" > } > ) > > +(define_insn "*aarch64_narrow_trunc<mode>" > + [(set (match_operand:<VNARROWQ2> 0 "register_operand" "=w") > + (vec_concat:<VNARROWQ2> > + (truncate:<VNARROWQ> > + (match_operand:VQN 1 "register_operand" "w")) > + (truncate:<VNARROWQ> > + (match_operand:VQN 2 "register_operand" "w"))))] > + "TARGET_SIMD" > + "uzp1\\t%0.<V2ntype>, %1.<V2ntype>, %2.<V2ntype>" > + [(set_attr "type" "neon_permute<q>")] > +) > + > ;; Packing doubles. > > (define_expand "vec_pack_trunc_<mode>" > diff --git a/gcc/config/aarch64/iterators.md > b/gcc/config/aarch64/iterators.md > index > 8dbeed3b0d4a44cdc17dd333ed397b39a33f386a..95b385c0c9405fe95fcd072 > 62a9471ab13d5488e 100644 > --- a/gcc/config/aarch64/iterators.md > +++ b/gcc/config/aarch64/iterators.md > @@ -270,6 +270,14 @@ (define_mode_iterator VDQHS [V4HI V8HI V2SI > V4SI]) > ;; Advanced SIMD modes for H, S and D types. > (define_mode_iterator VDQHSD [V4HI V8HI V2SI V4SI V2DI]) > > +;; Modes for which we can narrow the element and increase the lane counts > +;; to preserve the same register size. > +(define_mode_attr VNARROWSIMD [(V4HI "V8QI") (V8HI "V16QI") (V4SI > "V8HI") > + (V2SI "V4HI") (V2DI "V4SI")]) > + > +(define_mode_attr Vnarrowsimd [(V4HI "v8qi") (V8HI "v16qi") (V4SI "v8hi") > + (V2SI "v4hi") (V2DI "v4si")]) > + > ;; Advanced SIMD and scalar integer modes for H and S. > (define_mode_iterator VSDQ_HSI [V4HI V8HI V2SI V4SI HI SI]) > > diff --git a/gcc/testsuite/gcc.target/aarch64/narrow_high_combine.c > b/gcc/testsuite/gcc.target/aarch64/narrow_high_combine.c > index > 50ecab002a3552d37a5cc0d8921f42f6c3dba195..fa61196d3644caa48b12151e > 12b15dfeab8c7e71 100644 > --- a/gcc/testsuite/gcc.target/aarch64/narrow_high_combine.c > +++ b/gcc/testsuite/gcc.target/aarch64/narrow_high_combine.c > @@ -225,7 +225,8 @@ TEST_2_UNARY (vqmovun, uint32x4_t, int64x2_t, > s64, u32) > /* { dg-final { scan-assembler-times "\\tuqshrn2\\tv" 6} } */ > /* { dg-final { scan-assembler-times "\\tsqrshrn2\\tv" 6} } */ > /* { dg-final { scan-assembler-times "\\tuqrshrn2\\tv" 6} } */ > -/* { dg-final { scan-assembler-times "\\txtn2\\tv" 12} } */ > +/* { dg-final { scan-assembler-times "\\txtn2\\tv" 6} } */ > +/* { dg-final { scan-assembler-times "\\tuzp1\\tv" 6} } */ > /* { dg-final { scan-assembler-times "\\tuqxtn2\\tv" 6} } */ > /* { dg-final { scan-assembler-times "\\tsqxtn2\\tv" 6} } */ > /* { dg-final { scan-assembler-times "\\tsqxtun2\\tv" 6} } */ > diff --git a/gcc/testsuite/gcc.target/aarch64/xtn-combine-1.c > b/gcc/testsuite/gcc.target/aarch64/xtn-combine-1.c > new file mode 100644 > index > 0000000000000000000000000000000000000000..ed655cc970a602da4ace78d > c8dbd64ab18b0d4ab > --- /dev/null > +++ b/gcc/testsuite/gcc.target/aarch64/xtn-combine-1.c > @@ -0,0 +1,12 @@ > +/* { dg-do assemble } */ > +/* { dg-options "-O3 --save-temps --param=vect-epilogues-nomask=0" } */ > + > +void d2 (short * restrict a, int *b, int n) > +{ > + for (int i = 0; i < n; i++) > + a[i] = b[i]; > +} > + > +/* { dg-final { scan-assembler-times {\tuzp1\t} 1 } } */ > +/* { dg-final { scan-assembler-not {\txtn\t} } } */ > +/* { dg-final { scan-assembler-not {\txtn2\t} } } */ > > > --
Hi All,
This is a new version with BE support and more tests.
Bootstrapped Regtested on aarch64-none-linux-gnu and no issues.
Ok for master?
Thanks,
Tamar
gcc/ChangeLog:
* config/aarch64/aarch64-simd.md (*aarch64_narrow_trunc<mode>_le):
(*aarch64_narrow_trunc<mode>_be): New.
* config/aarch64/iterators.md (VNARROWSIMD, Vnarrowsimd): New.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/narrow_high_combine.c: Update case.
* gcc.target/aarch64/xtn-combine-1.c: New test.
* gcc.target/aarch64/xtn-combine-2.c: New test.
* gcc.target/aarch64/xtn-combine-3.c: New test.
* gcc.target/aarch64/xtn-combine-4.c: New test.
* gcc.target/aarch64/xtn-combine-5.c: New test.
* gcc.target/aarch64/xtn-combine-6.c: New test.
--- inline copy of patch ---
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index 0b340b49fa06684b80d0b78cb712e49328ca92d5..8435dece660a12aa747c4a489fbbda5bc0f83a86 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -1753,6 +1753,30 @@ (define_expand "aarch64_xtn2<mode>"
}
)
+(define_insn "*aarch64_narrow_trunc<mode>_le"
+ [(set (match_operand:<VNARROWQ2> 0 "register_operand" "=w")
+ (vec_concat:<VNARROWQ2>
+ (truncate:<VNARROWQ>
+ (match_operand:VQN 1 "register_operand" "w"))
+ (truncate:<VNARROWQ>
+ (match_operand:VQN 2 "register_operand" "w"))))]
+ "TARGET_SIMD && !BYTES_BIG_ENDIAN"
+ "uzp1\\t%0.<V2ntype>, %1.<V2ntype>, %2.<V2ntype>"
+ [(set_attr "type" "neon_permute<q>")]
+)
+
+(define_insn "*aarch64_narrow_trunc<mode>_be"
+ [(set (match_operand:<VNARROWQ2> 0 "register_operand" "=w")
+ (vec_concat:<VNARROWQ2>
+ (truncate:<VNARROWQ>
+ (match_operand:VQN 2 "register_operand" "w"))
+ (truncate:<VNARROWQ>
+ (match_operand:VQN 1 "register_operand" "w"))))]
+ "TARGET_SIMD && BYTES_BIG_ENDIAN"
+ "uzp1\\t%0.<V2ntype>, %1.<V2ntype>, %2.<V2ntype>"
+ [(set_attr "type" "neon_permute<q>")]
+)
+
;; Packing doubles.
(define_expand "vec_pack_trunc_<mode>"
diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md
index 8dbeed3b0d4a44cdc17dd333ed397b39a33f386a..95b385c0c9405fe95fcd07262a9471ab13d5488e 100644
--- a/gcc/config/aarch64/iterators.md
+++ b/gcc/config/aarch64/iterators.md
@@ -270,6 +270,14 @@ (define_mode_iterator VDQHS [V4HI V8HI V2SI V4SI])
;; Advanced SIMD modes for H, S and D types.
(define_mode_iterator VDQHSD [V4HI V8HI V2SI V4SI V2DI])
+;; Modes for which we can narrow the element and increase the lane counts
+;; to preserve the same register size.
+(define_mode_attr VNARROWSIMD [(V4HI "V8QI") (V8HI "V16QI") (V4SI "V8HI")
+ (V2SI "V4HI") (V2DI "V4SI")])
+
+(define_mode_attr Vnarrowsimd [(V4HI "v8qi") (V8HI "v16qi") (V4SI "v8hi")
+ (V2SI "v4hi") (V2DI "v4si")])
+
;; Advanced SIMD and scalar integer modes for H and S.
(define_mode_iterator VSDQ_HSI [V4HI V8HI V2SI V4SI HI SI])
diff --git a/gcc/testsuite/gcc.target/aarch64/narrow_high_combine.c b/gcc/testsuite/gcc.target/aarch64/narrow_high_combine.c
index 50ecab002a3552d37a5cc0d8921f42f6c3dba195..fa61196d3644caa48b12151e12b15dfeab8c7e71 100644
--- a/gcc/testsuite/gcc.target/aarch64/narrow_high_combine.c
+++ b/gcc/testsuite/gcc.target/aarch64/narrow_high_combine.c
@@ -225,7 +225,8 @@ TEST_2_UNARY (vqmovun, uint32x4_t, int64x2_t, s64, u32)
/* { dg-final { scan-assembler-times "\\tuqshrn2\\tv" 6} } */
/* { dg-final { scan-assembler-times "\\tsqrshrn2\\tv" 6} } */
/* { dg-final { scan-assembler-times "\\tuqrshrn2\\tv" 6} } */
-/* { dg-final { scan-assembler-times "\\txtn2\\tv" 12} } */
+/* { dg-final { scan-assembler-times "\\txtn2\\tv" 6} } */
+/* { dg-final { scan-assembler-times "\\tuzp1\\tv" 6} } */
/* { dg-final { scan-assembler-times "\\tuqxtn2\\tv" 6} } */
/* { dg-final { scan-assembler-times "\\tsqxtn2\\tv" 6} } */
/* { dg-final { scan-assembler-times "\\tsqxtun2\\tv" 6} } */
diff --git a/gcc/testsuite/gcc.target/aarch64/xtn-combine-1.c b/gcc/testsuite/gcc.target/aarch64/xtn-combine-1.c
new file mode 100644
index 0000000000000000000000000000000000000000..14e0414cd1478f1cb7b17766aa8d4451c5659977
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/xtn-combine-1.c
@@ -0,0 +1,16 @@
+/* { dg-do assemble } */
+/* { dg-options "-O3 --save-temps --param=vect-epilogues-nomask=0" } */
+
+#define SIGN signed
+#define TYPE1 char
+#define TYPE2 short
+
+void d2 (SIGN TYPE1 * restrict a, SIGN TYPE2 *b, int n)
+{
+ for (int i = 0; i < n; i++)
+ a[i] = b[i];
+}
+
+/* { dg-final { scan-assembler-times {\tuzp1\t} 1 } } */
+/* { dg-final { scan-assembler-not {\txtn\t} } } */
+/* { dg-final { scan-assembler-not {\txtn2\t} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/xtn-combine-2.c b/gcc/testsuite/gcc.target/aarch64/xtn-combine-2.c
new file mode 100644
index 0000000000000000000000000000000000000000..c259010442bca4ba008706e47b3ffcc50a910b52
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/xtn-combine-2.c
@@ -0,0 +1,16 @@
+/* { dg-do assemble } */
+/* { dg-options "-O3 --save-temps --param=vect-epilogues-nomask=0" } */
+
+#define SIGN signed
+#define TYPE1 short
+#define TYPE2 int
+
+void d2 (SIGN TYPE1 * restrict a, SIGN TYPE2 *b, int n)
+{
+ for (int i = 0; i < n; i++)
+ a[i] = b[i];
+}
+
+/* { dg-final { scan-assembler-times {\tuzp1\t} 1 } } */
+/* { dg-final { scan-assembler-not {\txtn\t} } } */
+/* { dg-final { scan-assembler-not {\txtn2\t} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/xtn-combine-3.c b/gcc/testsuite/gcc.target/aarch64/xtn-combine-3.c
new file mode 100644
index 0000000000000000000000000000000000000000..9a2065f65101f82ebe33519840919f9606192c43
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/xtn-combine-3.c
@@ -0,0 +1,16 @@
+/* { dg-do assemble } */
+/* { dg-options "-O3 --save-temps --param=vect-epilogues-nomask=0" } */
+
+#define SIGN signed
+#define TYPE1 int
+#define TYPE2 long long
+
+void d2 (SIGN TYPE1 * restrict a, SIGN TYPE2 *b, int n)
+{
+ for (int i = 0; i < n; i++)
+ a[i] = b[i];
+}
+
+/* { dg-final { scan-assembler-times {\tuzp1\t} 1 } } */
+/* { dg-final { scan-assembler-not {\txtn\t} } } */
+/* { dg-final { scan-assembler-not {\txtn2\t} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/xtn-combine-4.c b/gcc/testsuite/gcc.target/aarch64/xtn-combine-4.c
new file mode 100644
index 0000000000000000000000000000000000000000..77c3dce12049989d344e4652bd593de2e846ae25
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/xtn-combine-4.c
@@ -0,0 +1,16 @@
+/* { dg-do assemble } */
+/* { dg-options "-O3 --save-temps --param=vect-epilogues-nomask=0" } */
+
+#define SIGN unsigned
+#define TYPE1 char
+#define TYPE2 short
+
+void d2 (SIGN TYPE1 * restrict a, SIGN TYPE2 *b, int n)
+{
+ for (int i = 0; i < n; i++)
+ a[i] = b[i];
+}
+
+/* { dg-final { scan-assembler-times {\tuzp1\t} 1 } } */
+/* { dg-final { scan-assembler-not {\txtn\t} } } */
+/* { dg-final { scan-assembler-not {\txtn2\t} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/xtn-combine-5.c b/gcc/testsuite/gcc.target/aarch64/xtn-combine-5.c
new file mode 100644
index 0000000000000000000000000000000000000000..ae30e864ed7a239c40522423d7493ddd33830cc8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/xtn-combine-5.c
@@ -0,0 +1,16 @@
+/* { dg-do assemble } */
+/* { dg-options "-O3 --save-temps --param=vect-epilogues-nomask=0" } */
+
+#define SIGN unsigned
+#define TYPE1 short
+#define TYPE2 int
+
+void d2 (SIGN TYPE1 * restrict a, SIGN TYPE2 *b, int n)
+{
+ for (int i = 0; i < n; i++)
+ a[i] = b[i];
+}
+
+/* { dg-final { scan-assembler-times {\tuzp1\t} 1 } } */
+/* { dg-final { scan-assembler-not {\txtn\t} } } */
+/* { dg-final { scan-assembler-not {\txtn2\t} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/xtn-combine-6.c b/gcc/testsuite/gcc.target/aarch64/xtn-combine-6.c
new file mode 100644
index 0000000000000000000000000000000000000000..882f3d333e2cc42e964d880de5b58c505ec8b122
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/xtn-combine-6.c
@@ -0,0 +1,16 @@
+/* { dg-do assemble } */
+/* { dg-options "-O3 --save-temps --param=vect-epilogues-nomask=0" } */
+
+#define SIGN unsigned
+#define TYPE1 int
+#define TYPE2 long long
+
+void d2 (SIGN TYPE1 * restrict a, SIGN TYPE2 *b, int n)
+{
+ for (int i = 0; i < n; i++)
+ a[i] = b[i];
+}
+
+/* { dg-final { scan-assembler-times {\tuzp1\t} 1 } } */
+/* { dg-final { scan-assembler-not {\txtn\t} } } */
+/* { dg-final { scan-assembler-not {\txtn2\t} } } */
> -----Original Message----- > From: Tamar Christina <Tamar.Christina@arm.com> > Sent: Tuesday, October 12, 2021 5:25 PM > To: Kyrylo Tkachov <Kyrylo.Tkachov@arm.com>; gcc-patches@gcc.gnu.org > Cc: nd <nd@arm.com>; Richard Earnshaw <Richard.Earnshaw@arm.com>; > Marcus Shawcroft <Marcus.Shawcroft@arm.com>; Richard Sandiford > <Richard.Sandiford@arm.com> > Subject: RE: [PATCH 4/7]AArch64 Add pattern xtn+xtn2 to uzp2 > > Hi All, > > This is a new version with BE support and more tests. > > Bootstrapped Regtested on aarch64-none-linux-gnu and no issues. > > Ok for master? +(define_insn "*aarch64_narrow_trunc<mode>_le" + [(set (match_operand:<VNARROWQ2> 0 "register_operand" "=w") + (vec_concat:<VNARROWQ2> + (truncate:<VNARROWQ> + (match_operand:VQN 1 "register_operand" "w")) + (truncate:<VNARROWQ> + (match_operand:VQN 2 "register_operand" "w"))))] + "TARGET_SIMD && !BYTES_BIG_ENDIAN" + "uzp1\\t%0.<V2ntype>, %1.<V2ntype>, %2.<V2ntype>" + [(set_attr "type" "neon_permute<q>")] +) + +(define_insn "*aarch64_narrow_trunc<mode>_be" + [(set (match_operand:<VNARROWQ2> 0 "register_operand" "=w") + (vec_concat:<VNARROWQ2> + (truncate:<VNARROWQ> + (match_operand:VQN 2 "register_operand" "w")) + (truncate:<VNARROWQ> + (match_operand:VQN 1 "register_operand" "w"))))] + "TARGET_SIMD && BYTES_BIG_ENDIAN" + "uzp1\\t%0.<V2ntype>, %1.<V2ntype>, %2.<V2ntype>" + [(set_attr "type" "neon_permute<q>")] +) + Hmmm these patterns are identical in what they match they just have the effect of printing operands 1 and 2 in a different order. Perhaps it's more compact to change the output template into a BYTES_BIG_ENDIAN ? "uzp1\\t%0.<V2ntype>, %1.<V2ntype>, %2.<V2ntype>"" : uzp1\\t%0.<V2ntype>, %2.<V2ntype>, %1.<V2ntype>" and avoid having a second at all? Thanks, Kyrill > > Thanks, > Tamar > > gcc/ChangeLog: > > * config/aarch64/aarch64-simd.md > (*aarch64_narrow_trunc<mode>_le): > (*aarch64_narrow_trunc<mode>_be): New. > * config/aarch64/iterators.md (VNARROWSIMD, Vnarrowsimd): > New. > > gcc/testsuite/ChangeLog: > > * gcc.target/aarch64/narrow_high_combine.c: Update case. > * gcc.target/aarch64/xtn-combine-1.c: New test. > * gcc.target/aarch64/xtn-combine-2.c: New test. > * gcc.target/aarch64/xtn-combine-3.c: New test. > * gcc.target/aarch64/xtn-combine-4.c: New test. > * gcc.target/aarch64/xtn-combine-5.c: New test. > * gcc.target/aarch64/xtn-combine-6.c: New test. > > --- inline copy of patch --- > > diff --git a/gcc/config/aarch64/aarch64-simd.md > b/gcc/config/aarch64/aarch64-simd.md > index > 0b340b49fa06684b80d0b78cb712e49328ca92d5..8435dece660a12aa747c4a4 > 89fbbda5bc0f83a86 100644 > --- a/gcc/config/aarch64/aarch64-simd.md > +++ b/gcc/config/aarch64/aarch64-simd.md > @@ -1753,6 +1753,30 @@ (define_expand "aarch64_xtn2<mode>" > } > ) > > +(define_insn "*aarch64_narrow_trunc<mode>_le" > + [(set (match_operand:<VNARROWQ2> 0 "register_operand" "=w") > + (vec_concat:<VNARROWQ2> > + (truncate:<VNARROWQ> > + (match_operand:VQN 1 "register_operand" "w")) > + (truncate:<VNARROWQ> > + (match_operand:VQN 2 "register_operand" "w"))))] > + "TARGET_SIMD && !BYTES_BIG_ENDIAN" > + "uzp1\\t%0.<V2ntype>, %1.<V2ntype>, %2.<V2ntype>" > + [(set_attr "type" "neon_permute<q>")] > +) > + > +(define_insn "*aarch64_narrow_trunc<mode>_be" > + [(set (match_operand:<VNARROWQ2> 0 "register_operand" "=w") > + (vec_concat:<VNARROWQ2> > + (truncate:<VNARROWQ> > + (match_operand:VQN 2 "register_operand" "w")) > + (truncate:<VNARROWQ> > + (match_operand:VQN 1 "register_operand" "w"))))] > + "TARGET_SIMD && BYTES_BIG_ENDIAN" > + "uzp1\\t%0.<V2ntype>, %1.<V2ntype>, %2.<V2ntype>" > + [(set_attr "type" "neon_permute<q>")] > +) > + > ;; Packing doubles. > > (define_expand "vec_pack_trunc_<mode>" > diff --git a/gcc/config/aarch64/iterators.md > b/gcc/config/aarch64/iterators.md > index > 8dbeed3b0d4a44cdc17dd333ed397b39a33f386a..95b385c0c9405fe95fcd072 > 62a9471ab13d5488e 100644 > --- a/gcc/config/aarch64/iterators.md > +++ b/gcc/config/aarch64/iterators.md > @@ -270,6 +270,14 @@ (define_mode_iterator VDQHS [V4HI V8HI V2SI > V4SI]) > ;; Advanced SIMD modes for H, S and D types. > (define_mode_iterator VDQHSD [V4HI V8HI V2SI V4SI V2DI]) > > +;; Modes for which we can narrow the element and increase the lane counts > +;; to preserve the same register size. > +(define_mode_attr VNARROWSIMD [(V4HI "V8QI") (V8HI "V16QI") (V4SI > "V8HI") > + (V2SI "V4HI") (V2DI "V4SI")]) > + > +(define_mode_attr Vnarrowsimd [(V4HI "v8qi") (V8HI "v16qi") (V4SI "v8hi") > + (V2SI "v4hi") (V2DI "v4si")]) > + > ;; Advanced SIMD and scalar integer modes for H and S. > (define_mode_iterator VSDQ_HSI [V4HI V8HI V2SI V4SI HI SI]) > > diff --git a/gcc/testsuite/gcc.target/aarch64/narrow_high_combine.c > b/gcc/testsuite/gcc.target/aarch64/narrow_high_combine.c > index > 50ecab002a3552d37a5cc0d8921f42f6c3dba195..fa61196d3644caa48b12151e > 12b15dfeab8c7e71 100644 > --- a/gcc/testsuite/gcc.target/aarch64/narrow_high_combine.c > +++ b/gcc/testsuite/gcc.target/aarch64/narrow_high_combine.c > @@ -225,7 +225,8 @@ TEST_2_UNARY (vqmovun, uint32x4_t, int64x2_t, > s64, u32) > /* { dg-final { scan-assembler-times "\\tuqshrn2\\tv" 6} } */ > /* { dg-final { scan-assembler-times "\\tsqrshrn2\\tv" 6} } */ > /* { dg-final { scan-assembler-times "\\tuqrshrn2\\tv" 6} } */ > -/* { dg-final { scan-assembler-times "\\txtn2\\tv" 12} } */ > +/* { dg-final { scan-assembler-times "\\txtn2\\tv" 6} } */ > +/* { dg-final { scan-assembler-times "\\tuzp1\\tv" 6} } */ > /* { dg-final { scan-assembler-times "\\tuqxtn2\\tv" 6} } */ > /* { dg-final { scan-assembler-times "\\tsqxtn2\\tv" 6} } */ > /* { dg-final { scan-assembler-times "\\tsqxtun2\\tv" 6} } */ > diff --git a/gcc/testsuite/gcc.target/aarch64/xtn-combine-1.c > b/gcc/testsuite/gcc.target/aarch64/xtn-combine-1.c > new file mode 100644 > index > 0000000000000000000000000000000000000000..14e0414cd1478f1cb7b1776 > 6aa8d4451c5659977 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/aarch64/xtn-combine-1.c > @@ -0,0 +1,16 @@ > +/* { dg-do assemble } */ > +/* { dg-options "-O3 --save-temps --param=vect-epilogues-nomask=0" } */ > + > +#define SIGN signed > +#define TYPE1 char > +#define TYPE2 short > + > +void d2 (SIGN TYPE1 * restrict a, SIGN TYPE2 *b, int n) > +{ > + for (int i = 0; i < n; i++) > + a[i] = b[i]; > +} > + > +/* { dg-final { scan-assembler-times {\tuzp1\t} 1 } } */ > +/* { dg-final { scan-assembler-not {\txtn\t} } } */ > +/* { dg-final { scan-assembler-not {\txtn2\t} } } */ > diff --git a/gcc/testsuite/gcc.target/aarch64/xtn-combine-2.c > b/gcc/testsuite/gcc.target/aarch64/xtn-combine-2.c > new file mode 100644 > index > 0000000000000000000000000000000000000000..c259010442bca4ba008706e > 47b3ffcc50a910b52 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/aarch64/xtn-combine-2.c > @@ -0,0 +1,16 @@ > +/* { dg-do assemble } */ > +/* { dg-options "-O3 --save-temps --param=vect-epilogues-nomask=0" } */ > + > +#define SIGN signed > +#define TYPE1 short > +#define TYPE2 int > + > +void d2 (SIGN TYPE1 * restrict a, SIGN TYPE2 *b, int n) > +{ > + for (int i = 0; i < n; i++) > + a[i] = b[i]; > +} > + > +/* { dg-final { scan-assembler-times {\tuzp1\t} 1 } } */ > +/* { dg-final { scan-assembler-not {\txtn\t} } } */ > +/* { dg-final { scan-assembler-not {\txtn2\t} } } */ > diff --git a/gcc/testsuite/gcc.target/aarch64/xtn-combine-3.c > b/gcc/testsuite/gcc.target/aarch64/xtn-combine-3.c > new file mode 100644 > index > 0000000000000000000000000000000000000000..9a2065f65101f82ebe33519 > 840919f9606192c43 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/aarch64/xtn-combine-3.c > @@ -0,0 +1,16 @@ > +/* { dg-do assemble } */ > +/* { dg-options "-O3 --save-temps --param=vect-epilogues-nomask=0" } */ > + > +#define SIGN signed > +#define TYPE1 int > +#define TYPE2 long long > + > +void d2 (SIGN TYPE1 * restrict a, SIGN TYPE2 *b, int n) > +{ > + for (int i = 0; i < n; i++) > + a[i] = b[i]; > +} > + > +/* { dg-final { scan-assembler-times {\tuzp1\t} 1 } } */ > +/* { dg-final { scan-assembler-not {\txtn\t} } } */ > +/* { dg-final { scan-assembler-not {\txtn2\t} } } */ > diff --git a/gcc/testsuite/gcc.target/aarch64/xtn-combine-4.c > b/gcc/testsuite/gcc.target/aarch64/xtn-combine-4.c > new file mode 100644 > index > 0000000000000000000000000000000000000000..77c3dce12049989d344e465 > 2bd593de2e846ae25 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/aarch64/xtn-combine-4.c > @@ -0,0 +1,16 @@ > +/* { dg-do assemble } */ > +/* { dg-options "-O3 --save-temps --param=vect-epilogues-nomask=0" } */ > + > +#define SIGN unsigned > +#define TYPE1 char > +#define TYPE2 short > + > +void d2 (SIGN TYPE1 * restrict a, SIGN TYPE2 *b, int n) > +{ > + for (int i = 0; i < n; i++) > + a[i] = b[i]; > +} > + > +/* { dg-final { scan-assembler-times {\tuzp1\t} 1 } } */ > +/* { dg-final { scan-assembler-not {\txtn\t} } } */ > +/* { dg-final { scan-assembler-not {\txtn2\t} } } */ > diff --git a/gcc/testsuite/gcc.target/aarch64/xtn-combine-5.c > b/gcc/testsuite/gcc.target/aarch64/xtn-combine-5.c > new file mode 100644 > index > 0000000000000000000000000000000000000000..ae30e864ed7a239c4052242 > 3d7493ddd33830cc8 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/aarch64/xtn-combine-5.c > @@ -0,0 +1,16 @@ > +/* { dg-do assemble } */ > +/* { dg-options "-O3 --save-temps --param=vect-epilogues-nomask=0" } */ > + > +#define SIGN unsigned > +#define TYPE1 short > +#define TYPE2 int > + > +void d2 (SIGN TYPE1 * restrict a, SIGN TYPE2 *b, int n) > +{ > + for (int i = 0; i < n; i++) > + a[i] = b[i]; > +} > + > +/* { dg-final { scan-assembler-times {\tuzp1\t} 1 } } */ > +/* { dg-final { scan-assembler-not {\txtn\t} } } */ > +/* { dg-final { scan-assembler-not {\txtn2\t} } } */ > diff --git a/gcc/testsuite/gcc.target/aarch64/xtn-combine-6.c > b/gcc/testsuite/gcc.target/aarch64/xtn-combine-6.c > new file mode 100644 > index > 0000000000000000000000000000000000000000..882f3d333e2cc42e964d880 > de5b58c505ec8b122 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/aarch64/xtn-combine-6.c > @@ -0,0 +1,16 @@ > +/* { dg-do assemble } */ > +/* { dg-options "-O3 --save-temps --param=vect-epilogues-nomask=0" } */ > + > +#define SIGN unsigned > +#define TYPE1 int > +#define TYPE2 long long > + > +void d2 (SIGN TYPE1 * restrict a, SIGN TYPE2 *b, int n) > +{ > + for (int i = 0; i < n; i++) > + a[i] = b[i]; > +} > + > +/* { dg-final { scan-assembler-times {\tuzp1\t} 1 } } */ > +/* { dg-final { scan-assembler-not {\txtn\t} } } */ > +/* { dg-final { scan-assembler-not {\txtn2\t} } } */
> > Hmmm these patterns are identical in what they match they just have the > effect of printing operands 1 and 2 in a different order. > Perhaps it's more compact to change the output template into a > BYTES_BIG_ENDIAN ? > "uzp1\\t%0.<V2ntype>, %1.<V2ntype>, %2.<V2ntype>"" : > uzp1\\t%0.<V2ntype>, %2.<V2ntype>, %1.<V2ntype>" > and avoid having a second at all? > Bootstrapped Regtested on aarch64-none-linux-gnu and no issues. Ok for master? Thanks, Tamar gcc/ChangeLog: * config/aarch64/aarch64-simd.md (*aarch64_narrow_trunc<mode>): New. * config/aarch64/iterators.md (VNARROWSIMD, Vnarrowsimd): New. gcc/testsuite/ChangeLog: * gcc.target/aarch64/narrow_high_combine.c: Update case. * gcc.target/aarch64/xtn-combine-1.c: New test. * gcc.target/aarch64/xtn-combine-2.c: New test. * gcc.target/aarch64/xtn-combine-3.c: New test. * gcc.target/aarch64/xtn-combine-4.c: New test. * gcc.target/aarch64/xtn-combine-5.c: New test. * gcc.target/aarch64/xtn-combine-6.c: New test. --- inline copy of patch --- diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 0b340b49fa06684b80d0b78cb712e49328ca92d5..b0dda554466149817a7828dbf4e0ed372a91872b 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -1753,6 +1753,23 @@ (define_expand "aarch64_xtn2<mode>" } ) +(define_insn "*aarch64_narrow_trunc<mode>" + [(set (match_operand:<VNARROWQ2> 0 "register_operand" "=w") + (vec_concat:<VNARROWQ2> + (truncate:<VNARROWQ> + (match_operand:VQN 1 "register_operand" "w")) + (truncate:<VNARROWQ> + (match_operand:VQN 2 "register_operand" "w"))))] + "TARGET_SIMD" +{ + if (!BYTES_BIG_ENDIAN) + return "uzp1\\t%0.<V2ntype>, %1.<V2ntype>, %2.<V2ntype>"; + else + return "uzp1\\t%0.<V2ntype>, %2.<V2ntype>, %1.<V2ntype>"; +} + [(set_attr "type" "neon_permute<q>")] +) + ;; Packing doubles. (define_expand "vec_pack_trunc_<mode>" diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index 8dbeed3b0d4a44cdc17dd333ed397b39a33f386a..95b385c0c9405fe95fcd07262a9471ab13d5488e 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -270,6 +270,14 @@ (define_mode_iterator VDQHS [V4HI V8HI V2SI V4SI]) ;; Advanced SIMD modes for H, S and D types. (define_mode_iterator VDQHSD [V4HI V8HI V2SI V4SI V2DI]) +;; Modes for which we can narrow the element and increase the lane counts +;; to preserve the same register size. +(define_mode_attr VNARROWSIMD [(V4HI "V8QI") (V8HI "V16QI") (V4SI "V8HI") + (V2SI "V4HI") (V2DI "V4SI")]) + +(define_mode_attr Vnarrowsimd [(V4HI "v8qi") (V8HI "v16qi") (V4SI "v8hi") + (V2SI "v4hi") (V2DI "v4si")]) + ;; Advanced SIMD and scalar integer modes for H and S. (define_mode_iterator VSDQ_HSI [V4HI V8HI V2SI V4SI HI SI]) diff --git a/gcc/testsuite/gcc.target/aarch64/narrow_high_combine.c b/gcc/testsuite/gcc.target/aarch64/narrow_high_combine.c index 50ecab002a3552d37a5cc0d8921f42f6c3dba195..fa61196d3644caa48b12151e12b15dfeab8c7e71 100644 --- a/gcc/testsuite/gcc.target/aarch64/narrow_high_combine.c +++ b/gcc/testsuite/gcc.target/aarch64/narrow_high_combine.c @@ -225,7 +225,8 @@ TEST_2_UNARY (vqmovun, uint32x4_t, int64x2_t, s64, u32) /* { dg-final { scan-assembler-times "\\tuqshrn2\\tv" 6} } */ /* { dg-final { scan-assembler-times "\\tsqrshrn2\\tv" 6} } */ /* { dg-final { scan-assembler-times "\\tuqrshrn2\\tv" 6} } */ -/* { dg-final { scan-assembler-times "\\txtn2\\tv" 12} } */ +/* { dg-final { scan-assembler-times "\\txtn2\\tv" 6} } */ +/* { dg-final { scan-assembler-times "\\tuzp1\\tv" 6} } */ /* { dg-final { scan-assembler-times "\\tuqxtn2\\tv" 6} } */ /* { dg-final { scan-assembler-times "\\tsqxtn2\\tv" 6} } */ /* { dg-final { scan-assembler-times "\\tsqxtun2\\tv" 6} } */ diff --git a/gcc/testsuite/gcc.target/aarch64/xtn-combine-1.c b/gcc/testsuite/gcc.target/aarch64/xtn-combine-1.c new file mode 100644 index 0000000000000000000000000000000000000000..14e0414cd1478f1cb7b17766aa8d4451c5659977 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/xtn-combine-1.c @@ -0,0 +1,16 @@ +/* { dg-do assemble } */ +/* { dg-options "-O3 --save-temps --param=vect-epilogues-nomask=0" } */ + +#define SIGN signed +#define TYPE1 char +#define TYPE2 short + +void d2 (SIGN TYPE1 * restrict a, SIGN TYPE2 *b, int n) +{ + for (int i = 0; i < n; i++) + a[i] = b[i]; +} + +/* { dg-final { scan-assembler-times {\tuzp1\t} 1 } } */ +/* { dg-final { scan-assembler-not {\txtn\t} } } */ +/* { dg-final { scan-assembler-not {\txtn2\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/xtn-combine-2.c b/gcc/testsuite/gcc.target/aarch64/xtn-combine-2.c new file mode 100644 index 0000000000000000000000000000000000000000..c259010442bca4ba008706e47b3ffcc50a910b52 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/xtn-combine-2.c @@ -0,0 +1,16 @@ +/* { dg-do assemble } */ +/* { dg-options "-O3 --save-temps --param=vect-epilogues-nomask=0" } */ + +#define SIGN signed +#define TYPE1 short +#define TYPE2 int + +void d2 (SIGN TYPE1 * restrict a, SIGN TYPE2 *b, int n) +{ + for (int i = 0; i < n; i++) + a[i] = b[i]; +} + +/* { dg-final { scan-assembler-times {\tuzp1\t} 1 } } */ +/* { dg-final { scan-assembler-not {\txtn\t} } } */ +/* { dg-final { scan-assembler-not {\txtn2\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/xtn-combine-3.c b/gcc/testsuite/gcc.target/aarch64/xtn-combine-3.c new file mode 100644 index 0000000000000000000000000000000000000000..9a2065f65101f82ebe33519840919f9606192c43 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/xtn-combine-3.c @@ -0,0 +1,16 @@ +/* { dg-do assemble } */ +/* { dg-options "-O3 --save-temps --param=vect-epilogues-nomask=0" } */ + +#define SIGN signed +#define TYPE1 int +#define TYPE2 long long + +void d2 (SIGN TYPE1 * restrict a, SIGN TYPE2 *b, int n) +{ + for (int i = 0; i < n; i++) + a[i] = b[i]; +} + +/* { dg-final { scan-assembler-times {\tuzp1\t} 1 } } */ +/* { dg-final { scan-assembler-not {\txtn\t} } } */ +/* { dg-final { scan-assembler-not {\txtn2\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/xtn-combine-4.c b/gcc/testsuite/gcc.target/aarch64/xtn-combine-4.c new file mode 100644 index 0000000000000000000000000000000000000000..77c3dce12049989d344e4652bd593de2e846ae25 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/xtn-combine-4.c @@ -0,0 +1,16 @@ +/* { dg-do assemble } */ +/* { dg-options "-O3 --save-temps --param=vect-epilogues-nomask=0" } */ + +#define SIGN unsigned +#define TYPE1 char +#define TYPE2 short + +void d2 (SIGN TYPE1 * restrict a, SIGN TYPE2 *b, int n) +{ + for (int i = 0; i < n; i++) + a[i] = b[i]; +} + +/* { dg-final { scan-assembler-times {\tuzp1\t} 1 } } */ +/* { dg-final { scan-assembler-not {\txtn\t} } } */ +/* { dg-final { scan-assembler-not {\txtn2\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/xtn-combine-5.c b/gcc/testsuite/gcc.target/aarch64/xtn-combine-5.c new file mode 100644 index 0000000000000000000000000000000000000000..ae30e864ed7a239c40522423d7493ddd33830cc8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/xtn-combine-5.c @@ -0,0 +1,16 @@ +/* { dg-do assemble } */ +/* { dg-options "-O3 --save-temps --param=vect-epilogues-nomask=0" } */ + +#define SIGN unsigned +#define TYPE1 short +#define TYPE2 int + +void d2 (SIGN TYPE1 * restrict a, SIGN TYPE2 *b, int n) +{ + for (int i = 0; i < n; i++) + a[i] = b[i]; +} + +/* { dg-final { scan-assembler-times {\tuzp1\t} 1 } } */ +/* { dg-final { scan-assembler-not {\txtn\t} } } */ +/* { dg-final { scan-assembler-not {\txtn2\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/xtn-combine-6.c b/gcc/testsuite/gcc.target/aarch64/xtn-combine-6.c new file mode 100644 index 0000000000000000000000000000000000000000..882f3d333e2cc42e964d880de5b58c505ec8b122 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/xtn-combine-6.c @@ -0,0 +1,16 @@ +/* { dg-do assemble } */ +/* { dg-options "-O3 --save-temps --param=vect-epilogues-nomask=0" } */ + +#define SIGN unsigned +#define TYPE1 int +#define TYPE2 long long + +void d2 (SIGN TYPE1 * restrict a, SIGN TYPE2 *b, int n) +{ + for (int i = 0; i < n; i++) + a[i] = b[i]; +} + +/* { dg-final { scan-assembler-times {\tuzp1\t} 1 } } */ +/* { dg-final { scan-assembler-not {\txtn\t} } } */ +/* { dg-final { scan-assembler-not {\txtn2\t} } } */
> -----Original Message----- > From: Tamar Christina <Tamar.Christina@arm.com> > Sent: Wednesday, October 13, 2021 12:06 PM > To: Kyrylo Tkachov <Kyrylo.Tkachov@arm.com>; gcc-patches@gcc.gnu.org > Cc: nd <nd@arm.com>; Richard Earnshaw <Richard.Earnshaw@arm.com>; > Marcus Shawcroft <Marcus.Shawcroft@arm.com>; Richard Sandiford > <Richard.Sandiford@arm.com> > Subject: RE: [PATCH 4/7]AArch64 Add pattern xtn+xtn2 to uzp2 > > > > > Hmmm these patterns are identical in what they match they just have the > > effect of printing operands 1 and 2 in a different order. > > Perhaps it's more compact to change the output template into a > > BYTES_BIG_ENDIAN ? > > "uzp1\\t%0.<V2ntype>, %1.<V2ntype>, %2.<V2ntype>"" : > > uzp1\\t%0.<V2ntype>, %2.<V2ntype>, %1.<V2ntype>" > > and avoid having a second at all? > > > > Bootstrapped Regtested on aarch64-none-linux-gnu and no issues. > > Ok for master? Sorry I should have noticed earlier but... diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index 8dbeed3b0d4a44cdc17dd333ed397b39a33f386a..95b385c0c9405fe95fcd07262a9471ab13d5488e 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -270,6 +270,14 @@ (define_mode_iterator VDQHS [V4HI V8HI V2SI V4SI]) ;; Advanced SIMD modes for H, S and D types. (define_mode_iterator VDQHSD [V4HI V8HI V2SI V4SI V2DI]) +;; Modes for which we can narrow the element and increase the lane counts +;; to preserve the same register size. +(define_mode_attr VNARROWSIMD [(V4HI "V8QI") (V8HI "V16QI") (V4SI "V8HI") + (V2SI "V4HI") (V2DI "V4SI")]) + +(define_mode_attr Vnarrowsimd [(V4HI "v8qi") (V8HI "v16qi") (V4SI "v8hi") + (V2SI "v4hi") (V2DI "v4si")]) + These attributes are not needed it seems. So patch is ok without this hunk. Thanks, Kyrill > > Thanks, > Tamar > > gcc/ChangeLog: > > * config/aarch64/aarch64-simd.md > (*aarch64_narrow_trunc<mode>): New. > * config/aarch64/iterators.md (VNARROWSIMD, Vnarrowsimd): > New. > > gcc/testsuite/ChangeLog: > > * gcc.target/aarch64/narrow_high_combine.c: Update case. > * gcc.target/aarch64/xtn-combine-1.c: New test. > * gcc.target/aarch64/xtn-combine-2.c: New test. > * gcc.target/aarch64/xtn-combine-3.c: New test. > * gcc.target/aarch64/xtn-combine-4.c: New test. > * gcc.target/aarch64/xtn-combine-5.c: New test. > * gcc.target/aarch64/xtn-combine-6.c: New test. > > --- inline copy of patch --- > > diff --git a/gcc/config/aarch64/aarch64-simd.md > b/gcc/config/aarch64/aarch64-simd.md > index > 0b340b49fa06684b80d0b78cb712e49328ca92d5..b0dda554466149817a7828 > dbf4e0ed372a91872b 100644 > --- a/gcc/config/aarch64/aarch64-simd.md > +++ b/gcc/config/aarch64/aarch64-simd.md > @@ -1753,6 +1753,23 @@ (define_expand "aarch64_xtn2<mode>" > } > ) > > +(define_insn "*aarch64_narrow_trunc<mode>" > + [(set (match_operand:<VNARROWQ2> 0 "register_operand" "=w") > + (vec_concat:<VNARROWQ2> > + (truncate:<VNARROWQ> > + (match_operand:VQN 1 "register_operand" "w")) > + (truncate:<VNARROWQ> > + (match_operand:VQN 2 "register_operand" "w"))))] > + "TARGET_SIMD" > +{ > + if (!BYTES_BIG_ENDIAN) > + return "uzp1\\t%0.<V2ntype>, %1.<V2ntype>, %2.<V2ntype>"; > + else > + return "uzp1\\t%0.<V2ntype>, %2.<V2ntype>, %1.<V2ntype>"; > +} > + [(set_attr "type" "neon_permute<q>")] > +) > + > ;; Packing doubles. > > (define_expand "vec_pack_trunc_<mode>" > diff --git a/gcc/config/aarch64/iterators.md > b/gcc/config/aarch64/iterators.md > index > 8dbeed3b0d4a44cdc17dd333ed397b39a33f386a..95b385c0c9405fe95fcd072 > 62a9471ab13d5488e 100644 > --- a/gcc/config/aarch64/iterators.md > +++ b/gcc/config/aarch64/iterators.md > @@ -270,6 +270,14 @@ (define_mode_iterator VDQHS [V4HI V8HI V2SI > V4SI]) > ;; Advanced SIMD modes for H, S and D types. > (define_mode_iterator VDQHSD [V4HI V8HI V2SI V4SI V2DI]) > > +;; Modes for which we can narrow the element and increase the lane counts > +;; to preserve the same register size. > +(define_mode_attr VNARROWSIMD [(V4HI "V8QI") (V8HI "V16QI") (V4SI > "V8HI") > + (V2SI "V4HI") (V2DI "V4SI")]) > + > +(define_mode_attr Vnarrowsimd [(V4HI "v8qi") (V8HI "v16qi") (V4SI "v8hi") > + (V2SI "v4hi") (V2DI "v4si")]) > + > ;; Advanced SIMD and scalar integer modes for H and S. > (define_mode_iterator VSDQ_HSI [V4HI V8HI V2SI V4SI HI SI]) > > diff --git a/gcc/testsuite/gcc.target/aarch64/narrow_high_combine.c > b/gcc/testsuite/gcc.target/aarch64/narrow_high_combine.c > index > 50ecab002a3552d37a5cc0d8921f42f6c3dba195..fa61196d3644caa48b12151e > 12b15dfeab8c7e71 100644 > --- a/gcc/testsuite/gcc.target/aarch64/narrow_high_combine.c > +++ b/gcc/testsuite/gcc.target/aarch64/narrow_high_combine.c > @@ -225,7 +225,8 @@ TEST_2_UNARY (vqmovun, uint32x4_t, int64x2_t, > s64, u32) > /* { dg-final { scan-assembler-times "\\tuqshrn2\\tv" 6} } */ > /* { dg-final { scan-assembler-times "\\tsqrshrn2\\tv" 6} } */ > /* { dg-final { scan-assembler-times "\\tuqrshrn2\\tv" 6} } */ > -/* { dg-final { scan-assembler-times "\\txtn2\\tv" 12} } */ > +/* { dg-final { scan-assembler-times "\\txtn2\\tv" 6} } */ > +/* { dg-final { scan-assembler-times "\\tuzp1\\tv" 6} } */ > /* { dg-final { scan-assembler-times "\\tuqxtn2\\tv" 6} } */ > /* { dg-final { scan-assembler-times "\\tsqxtn2\\tv" 6} } */ > /* { dg-final { scan-assembler-times "\\tsqxtun2\\tv" 6} } */ > diff --git a/gcc/testsuite/gcc.target/aarch64/xtn-combine-1.c > b/gcc/testsuite/gcc.target/aarch64/xtn-combine-1.c > new file mode 100644 > index > 0000000000000000000000000000000000000000..14e0414cd1478f1cb7b1776 > 6aa8d4451c5659977 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/aarch64/xtn-combine-1.c > @@ -0,0 +1,16 @@ > +/* { dg-do assemble } */ > +/* { dg-options "-O3 --save-temps --param=vect-epilogues-nomask=0" } */ > + > +#define SIGN signed > +#define TYPE1 char > +#define TYPE2 short > + > +void d2 (SIGN TYPE1 * restrict a, SIGN TYPE2 *b, int n) > +{ > + for (int i = 0; i < n; i++) > + a[i] = b[i]; > +} > + > +/* { dg-final { scan-assembler-times {\tuzp1\t} 1 } } */ > +/* { dg-final { scan-assembler-not {\txtn\t} } } */ > +/* { dg-final { scan-assembler-not {\txtn2\t} } } */ > diff --git a/gcc/testsuite/gcc.target/aarch64/xtn-combine-2.c > b/gcc/testsuite/gcc.target/aarch64/xtn-combine-2.c > new file mode 100644 > index > 0000000000000000000000000000000000000000..c259010442bca4ba008706e > 47b3ffcc50a910b52 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/aarch64/xtn-combine-2.c > @@ -0,0 +1,16 @@ > +/* { dg-do assemble } */ > +/* { dg-options "-O3 --save-temps --param=vect-epilogues-nomask=0" } */ > + > +#define SIGN signed > +#define TYPE1 short > +#define TYPE2 int > + > +void d2 (SIGN TYPE1 * restrict a, SIGN TYPE2 *b, int n) > +{ > + for (int i = 0; i < n; i++) > + a[i] = b[i]; > +} > + > +/* { dg-final { scan-assembler-times {\tuzp1\t} 1 } } */ > +/* { dg-final { scan-assembler-not {\txtn\t} } } */ > +/* { dg-final { scan-assembler-not {\txtn2\t} } } */ > diff --git a/gcc/testsuite/gcc.target/aarch64/xtn-combine-3.c > b/gcc/testsuite/gcc.target/aarch64/xtn-combine-3.c > new file mode 100644 > index > 0000000000000000000000000000000000000000..9a2065f65101f82ebe33519 > 840919f9606192c43 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/aarch64/xtn-combine-3.c > @@ -0,0 +1,16 @@ > +/* { dg-do assemble } */ > +/* { dg-options "-O3 --save-temps --param=vect-epilogues-nomask=0" } */ > + > +#define SIGN signed > +#define TYPE1 int > +#define TYPE2 long long > + > +void d2 (SIGN TYPE1 * restrict a, SIGN TYPE2 *b, int n) > +{ > + for (int i = 0; i < n; i++) > + a[i] = b[i]; > +} > + > +/* { dg-final { scan-assembler-times {\tuzp1\t} 1 } } */ > +/* { dg-final { scan-assembler-not {\txtn\t} } } */ > +/* { dg-final { scan-assembler-not {\txtn2\t} } } */ > diff --git a/gcc/testsuite/gcc.target/aarch64/xtn-combine-4.c > b/gcc/testsuite/gcc.target/aarch64/xtn-combine-4.c > new file mode 100644 > index > 0000000000000000000000000000000000000000..77c3dce12049989d344e465 > 2bd593de2e846ae25 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/aarch64/xtn-combine-4.c > @@ -0,0 +1,16 @@ > +/* { dg-do assemble } */ > +/* { dg-options "-O3 --save-temps --param=vect-epilogues-nomask=0" } */ > + > +#define SIGN unsigned > +#define TYPE1 char > +#define TYPE2 short > + > +void d2 (SIGN TYPE1 * restrict a, SIGN TYPE2 *b, int n) > +{ > + for (int i = 0; i < n; i++) > + a[i] = b[i]; > +} > + > +/* { dg-final { scan-assembler-times {\tuzp1\t} 1 } } */ > +/* { dg-final { scan-assembler-not {\txtn\t} } } */ > +/* { dg-final { scan-assembler-not {\txtn2\t} } } */ > diff --git a/gcc/testsuite/gcc.target/aarch64/xtn-combine-5.c > b/gcc/testsuite/gcc.target/aarch64/xtn-combine-5.c > new file mode 100644 > index > 0000000000000000000000000000000000000000..ae30e864ed7a239c4052242 > 3d7493ddd33830cc8 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/aarch64/xtn-combine-5.c > @@ -0,0 +1,16 @@ > +/* { dg-do assemble } */ > +/* { dg-options "-O3 --save-temps --param=vect-epilogues-nomask=0" } */ > + > +#define SIGN unsigned > +#define TYPE1 short > +#define TYPE2 int > + > +void d2 (SIGN TYPE1 * restrict a, SIGN TYPE2 *b, int n) > +{ > + for (int i = 0; i < n; i++) > + a[i] = b[i]; > +} > + > +/* { dg-final { scan-assembler-times {\tuzp1\t} 1 } } */ > +/* { dg-final { scan-assembler-not {\txtn\t} } } */ > +/* { dg-final { scan-assembler-not {\txtn2\t} } } */ > diff --git a/gcc/testsuite/gcc.target/aarch64/xtn-combine-6.c > b/gcc/testsuite/gcc.target/aarch64/xtn-combine-6.c > new file mode 100644 > index > 0000000000000000000000000000000000000000..882f3d333e2cc42e964d880 > de5b58c505ec8b122 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/aarch64/xtn-combine-6.c > @@ -0,0 +1,16 @@ > +/* { dg-do assemble } */ > +/* { dg-options "-O3 --save-temps --param=vect-epilogues-nomask=0" } */ > + > +#define SIGN unsigned > +#define TYPE1 int > +#define TYPE2 long long > + > +void d2 (SIGN TYPE1 * restrict a, SIGN TYPE2 *b, int n) > +{ > + for (int i = 0; i < n; i++) > + a[i] = b[i]; > +} > + > +/* { dg-final { scan-assembler-times {\tuzp1\t} 1 } } */ > +/* { dg-final { scan-assembler-not {\txtn\t} } } */ > +/* { dg-final { scan-assembler-not {\txtn2\t} } } */
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 36396ef236e8c476d5e2f1acee80dc54ec5ebe4e..33e3301d229366022a5b9481b6c3ae8f8d93f9e2 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -1753,6 +1753,18 @@ (define_expand "aarch64_xtn2<mode>" } ) +(define_insn "*aarch64_narrow_trunc<mode>" + [(set (match_operand:<VNARROWQ2> 0 "register_operand" "=w") + (vec_concat:<VNARROWQ2> + (truncate:<VNARROWQ> + (match_operand:VQN 1 "register_operand" "w")) + (truncate:<VNARROWQ> + (match_operand:VQN 2 "register_operand" "w"))))] + "TARGET_SIMD" + "uzp1\\t%0.<V2ntype>, %1.<V2ntype>, %2.<V2ntype>" + [(set_attr "type" "neon_permute<q>")] +) + ;; Packing doubles. (define_expand "vec_pack_trunc_<mode>" diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index 8dbeed3b0d4a44cdc17dd333ed397b39a33f386a..95b385c0c9405fe95fcd07262a9471ab13d5488e 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -270,6 +270,14 @@ (define_mode_iterator VDQHS [V4HI V8HI V2SI V4SI]) ;; Advanced SIMD modes for H, S and D types. (define_mode_iterator VDQHSD [V4HI V8HI V2SI V4SI V2DI]) +;; Modes for which we can narrow the element and increase the lane counts +;; to preserve the same register size. +(define_mode_attr VNARROWSIMD [(V4HI "V8QI") (V8HI "V16QI") (V4SI "V8HI") + (V2SI "V4HI") (V2DI "V4SI")]) + +(define_mode_attr Vnarrowsimd [(V4HI "v8qi") (V8HI "v16qi") (V4SI "v8hi") + (V2SI "v4hi") (V2DI "v4si")]) + ;; Advanced SIMD and scalar integer modes for H and S. (define_mode_iterator VSDQ_HSI [V4HI V8HI V2SI V4SI HI SI]) diff --git a/gcc/testsuite/gcc.target/aarch64/narrow_high_combine.c b/gcc/testsuite/gcc.target/aarch64/narrow_high_combine.c index 50ecab002a3552d37a5cc0d8921f42f6c3dba195..fa61196d3644caa48b12151e12b15dfeab8c7e71 100644 --- a/gcc/testsuite/gcc.target/aarch64/narrow_high_combine.c +++ b/gcc/testsuite/gcc.target/aarch64/narrow_high_combine.c @@ -225,7 +225,8 @@ TEST_2_UNARY (vqmovun, uint32x4_t, int64x2_t, s64, u32) /* { dg-final { scan-assembler-times "\\tuqshrn2\\tv" 6} } */ /* { dg-final { scan-assembler-times "\\tsqrshrn2\\tv" 6} } */ /* { dg-final { scan-assembler-times "\\tuqrshrn2\\tv" 6} } */ -/* { dg-final { scan-assembler-times "\\txtn2\\tv" 12} } */ +/* { dg-final { scan-assembler-times "\\txtn2\\tv" 6} } */ +/* { dg-final { scan-assembler-times "\\tuzp1\\tv" 6} } */ /* { dg-final { scan-assembler-times "\\tuqxtn2\\tv" 6} } */ /* { dg-final { scan-assembler-times "\\tsqxtn2\\tv" 6} } */ /* { dg-final { scan-assembler-times "\\tsqxtun2\\tv" 6} } */ diff --git a/gcc/testsuite/gcc.target/aarch64/xtn-combine-1.c b/gcc/testsuite/gcc.target/aarch64/xtn-combine-1.c new file mode 100644 index 0000000000000000000000000000000000000000..ed655cc970a602da4ace78dc8dbd64ab18b0d4ab --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/xtn-combine-1.c @@ -0,0 +1,12 @@ +/* { dg-do assemble } */ +/* { dg-options "-O3 --save-temps --param=vect-epilogues-nomask=0" } */ + +void d2 (short * restrict a, int *b, int n) +{ + for (int i = 0; i < n; i++) + a[i] = b[i]; +} + +/* { dg-final { scan-assembler-times {\tuzp1\t} 1 } } */ +/* { dg-final { scan-assembler-not {\txtn\t} } } */ +/* { dg-final { scan-assembler-not {\txtn2\t} } } */
Hi All, This turns truncate operations with a hi/lo pair into a single permute of half the bit size of the input and just ignoring the top bits (which are truncated out). i.e. void d2 (short * restrict a, int *b, int n) { for (int i = 0; i < n; i++) a[i] = b[i]; } now generates: .L4: ldp q0, q1, [x3] add x3, x3, 32 uzp1 v0.8h, v0.8h, v1.8h str q0, [x5], 16 cmp x4, x3 bne .L4 instead of .L4: ldp q0, q1, [x3] add x3, x3, 32 xtn v0.4h, v0.4s xtn2 v0.8h, v1.4s str q0, [x5], 16 cmp x4, x3 bne .L4 Bootstrapped Regtested on aarch64-none-linux-gnu and no issues. Ok for master? Thanks, Tamar gcc/ChangeLog: * config/aarch64/aarch64-simd.md (*aarch64_narrow_trunc<mode>): New. * config/aarch64/iterators.md (VNARROWSIMD, Vnarrowsimd): New. gcc/testsuite/ChangeLog: * gcc.target/aarch64/xtn-combine-1.c: New test. * gcc.target/aarch64/narrow_high_combine.c: Update case. --- inline copy of patch -- diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 36396ef236e8c476d5e2f1acee80dc54ec5ebe4e..33e3301d229366022a5b9481b6c3ae8f8d93f9e2 100644 --