| Message ID | 20210507075706.GH1179226@tucnak |
|---|---|
| State | New |
| Headers | show |
| Series | i386: Fix up 8-byte vcond* with -mxop [PR100445] | expand |
On Fri, May 7, 2021 at 9:57 AM Jakub Jelinek <jakub@redhat.com> wrote: > > Hi! > > ix86_expand_sse_movcc has special TARGET_XOP handling and the recent > addition of support of v*cond* patterns for MMXMODEI modes results in > ICEs because the expected pattern doesn't exist. We can handle it > using 128-bit vpcmov (if we ignore the upper 64 bits like we ignore in > other TARGET_MMX_WITH_SSE support). > > Bootstrapped/regtested on x86_64-linux and i686-linux (admittedly > on a CPU without XOP support), ok for trunk? > > 2021-05-07 Jakub Jelinek <jakub@redhat.com> > > PR target/100445 > * config/i386/mmx.md (*xop_pcmov_<mode>): New define_insn. > > * gcc.target/i386/pr100445.c: New test. OK. Thanks, Uros. > > --- gcc/config/i386/mmx.md.jj 2021-05-06 10:14:55.508063058 +0200 > +++ gcc/config/i386/mmx.md 2021-05-06 14:43:19.731486156 +0200 > @@ -1700,6 +1700,17 @@ (define_expand "vcond_mask_<mode><mode>" > DONE; > }) > > +;; XOP parallel XMM conditional moves > +(define_insn "*xop_pcmov_<mode>" > + [(set (match_operand:MMXMODEI 0 "register_operand" "=x") > + (if_then_else:MMXMODEI > + (match_operand:MMXMODEI 3 "register_operand" "x") > + (match_operand:MMXMODEI 1 "register_operand" "x") > + (match_operand:MMXMODEI 2 "register_operand" "x")))] > + "TARGET_XOP && TARGET_MMX_WITH_SSE" > + "vpcmov\t{%3, %2, %1, %0|%0, %1, %2, %3}" > + [(set_attr "type" "sse4arg")]) > + > ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; > ;; > ;; Parallel integral logical operations > --- gcc/testsuite/gcc.target/i386/pr100445.c.jj 2021-05-06 14:46:35.936327593 +0200 > +++ gcc/testsuite/gcc.target/i386/pr100445.c 2021-05-06 14:46:10.259609909 +0200 > @@ -0,0 +1,12 @@ > +/* PR target/100445 */ > +/* { dg-do compile } */ > +/* { dg-options "-O3 -mxop" } */ > + > +int a, b[3]; > + > +void > +foo (void) > +{ > + for (; a < 3; a++) > + b[a] = (a - 1) / 2; > +} > > Jakub >
--- gcc/config/i386/mmx.md.jj 2021-05-06 10:14:55.508063058 +0200 +++ gcc/config/i386/mmx.md 2021-05-06 14:43:19.731486156 +0200 @@ -1700,6 +1700,17 @@ (define_expand "vcond_mask_<mode><mode>" DONE; }) +;; XOP parallel XMM conditional moves +(define_insn "*xop_pcmov_<mode>" + [(set (match_operand:MMXMODEI 0 "register_operand" "=x") + (if_then_else:MMXMODEI + (match_operand:MMXMODEI 3 "register_operand" "x") + (match_operand:MMXMODEI 1 "register_operand" "x") + (match_operand:MMXMODEI 2 "register_operand" "x")))] + "TARGET_XOP && TARGET_MMX_WITH_SSE" + "vpcmov\t{%3, %2, %1, %0|%0, %1, %2, %3}" + [(set_attr "type" "sse4arg")]) + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; ;; Parallel integral logical operations --- gcc/testsuite/gcc.target/i386/pr100445.c.jj 2021-05-06 14:46:35.936327593 +0200 +++ gcc/testsuite/gcc.target/i386/pr100445.c 2021-05-06 14:46:10.259609909 +0200 @@ -0,0 +1,12 @@ +/* PR target/100445 */ +/* { dg-do compile } */ +/* { dg-options "-O3 -mxop" } */ + +int a, b[3]; + +void +foo (void) +{ + for (; a < 3; a++) + b[a] = (a - 1) / 2; +}