| Message ID | 20210407131451.pj6gmziyzvrmkd6b@arm.com |
|---|---|
| State | New |
| Headers | show |
| Series | [v2] arm: Various MVE vec_duplicate fixes [PR99647] | expand |
> -----Original Message----- > From: Alex Coplan <Alex.Coplan@arm.com> > Sent: 07 April 2021 14:15 > To: gcc-patches@gcc.gnu.org > Cc: nickc@redhat.com; Richard Earnshaw <Richard.Earnshaw@arm.com>; > Ramana Radhakrishnan <Ramana.Radhakrishnan@arm.com>; Kyrylo > Tkachov <Kyrylo.Tkachov@arm.com>; Richard Sandiford > <Richard.Sandiford@arm.com> > Subject: [PATCH v2] arm: Various MVE vec_duplicate fixes [PR99647] > > Hi, > > Here is a v2 of my previous attempt: > https://gcc.gnu.org/pipermail/gcc-patches/2021-April/567724.html > to fix this PR. > > --- > > This patch fixes various issues with vec_duplicate in the MVE patterns. > Currently there are two patterns named *mve_mov<mode>. The second of > these is really a vector duplicate rather than a move, so I've renamed > it accordingly. > > As it stands, there are several issues with this pattern: > 1. The MVE_types iterator has an entry for TImode, but > vec_duplicate:TI is invalid. > 2. The mode of the operand to vec_duplicate is SImode, but it should > vary according to the vector mode iterator. > 3. The second alternative of this pattern is bogus: it allows matching > symbol_refs (the cause of the PR) and const_ints (which means that it > matches (vec_duplicate (const_int ...)) which is non-canonical: such > rtxes should be const_vectors instead and handled by the main vector > move pattern). > > This patch fixes all of these issues, and removes the redundant > *mve_vec_duplicate<mode> pattern. > > Testing: > * Bootstrapped and regtested on arm-linux-gnueabihf, no regressions. > * Tested an arm-eabi cross configured with --with-float=hard > --with-arch=armv8.1-m.main+mve, no regressions. > > OK for trunk and eventual backport to GCC 10? Ok. Thanks, Kyrill > > Thanks, > Alex > > gcc/ChangeLog: > > PR target/99647 > * config/arm/iterators.md (MVE_vecs): New. > (V_elem): Also handle V2DF. > * config/arm/mve.md (*mve_mov<mode>): Rename to ... > (*mve_vdup<mode>): ... this. Remove second alternative since > vec_duplicate of const_int is not canonical RTL, and we don't > want to match symbol_refs. Fix up modes. > (*mve_vec_duplicate<mode>): Delete (pattern is redundant). > > gcc/testsuite/ChangeLog: > > PR target/99647 > * gcc.c-torture/compile/pr99647.c: New test.
diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md index 43aab2346c4..8fb723e65cd 100644 --- a/gcc/config/arm/iterators.md +++ b/gcc/config/arm/iterators.md @@ -261,6 +261,7 @@ (define_mode_iterator VBFCVTM [V2SI SF]) ;; MVE mode iterator. (define_mode_iterator MVE_types [V16QI V8HI V4SI V2DI TI V8HF V4SF V2DF]) +(define_mode_iterator MVE_vecs [V16QI V8HI V4SI V2DI V8HF V4SF V2DF]) (define_mode_iterator MVE_VLD_ST [V16QI V8HI V4SI V8HF V4SF]) (define_mode_iterator MVE_0 [V8HF V4SF]) (define_mode_iterator MVE_1 [V16QI V8HI V4SI V2DI]) @@ -567,9 +568,10 @@ (define_mode_attr V_elem [(V8QI "QI") (V16QI "QI") (V4HI "HI") (V8HI "HI") (V4HF "HF") (V8HF "HF") (V4BF "BF") (V8BF "BF") - (V2SI "SI") (V4SI "SI") - (V2SF "SF") (V4SF "SF") - (DI "DI") (V2DI "DI")]) + (V2SI "SI") (V4SI "SI") + (V2SF "SF") (V4SF "SF") + (DI "DI") (V2DI "DI") + (V2DF "DF")]) ;; As above but in lower case. (define_mode_attr V_elem_l [(V8QI "qi") (V16QI "qi") diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index 135186371e7..7467d5f4d57 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -104,18 +104,14 @@ (define_insn "*mve_mov<mode>" (set_attr "thumb2_pool_range" "*,*,*,*,1018,*,*,*,*") (set_attr "neg_pool_range" "*,*,*,*,996,*,*,*,*")]) -(define_insn "*mve_mov<mode>" - [(set (match_operand:MVE_types 0 "s_register_operand" "=w,w") - (vec_duplicate:MVE_types - (match_operand:SI 1 "nonmemory_operand" "r,i")))] +(define_insn "*mve_vdup<mode>" + [(set (match_operand:MVE_vecs 0 "s_register_operand" "=w") + (vec_duplicate:MVE_vecs + (match_operand:<V_elem> 1 "s_register_operand" "r")))] "TARGET_HAVE_MVE || TARGET_HAVE_MVE_FLOAT" -{ - if (which_alternative == 0) - return "vdup.<V_sz_elem>\t%q0, %1"; - return "vmov.<V_sz_elem>\t%q0, %1"; -} - [(set_attr "length" "4,4") - (set_attr "type" "mve_move,mve_move")]) + "vdup.<V_sz_elem>\t%q0, %1" + [(set_attr "length" "4") + (set_attr "type" "mve_move")]) ;; ;; [vst4q]) @@ -10737,13 +10733,6 @@ (define_insn "mve_vshlcq_m_<supf><mode>" [(set_attr "type" "mve_move") (set_attr "length" "8")]) -(define_insn "*mve_vec_duplicate<mode>" - [(set (match_operand:MVE_VLD_ST 0 "s_register_operand" "=w") - (vec_duplicate:MVE_VLD_ST (match_operand:<V_elem> 1 "general_operand" "r")))] - "TARGET_HAVE_MVE || TARGET_HAVE_MVE_FLOAT" - "vdup.<V_sz_elem>\t%q0, %1" - [(set_attr "type" "mve_move")]) - ;; CDE instructions on MVE registers. (define_insn "arm_vcx1qv16qi" diff --git a/gcc/testsuite/gcc.c-torture/compile/pr99647.c b/gcc/testsuite/gcc.c-torture/compile/pr99647.c new file mode 100644 index 00000000000..701155dd856 --- /dev/null +++ b/gcc/testsuite/gcc.c-torture/compile/pr99647.c @@ -0,0 +1,5 @@ +/* { dg-do assemble } */ +typedef int __attribute((vector_size(16))) V; +V f(void) { + return (V){ (int)f, (int)f, (int)f, (int)f }; +}