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[v3,5/6] RISC-V: Update shift-shift-5.c testcase for big endian

Message ID 20210224214300.30921-6-marcus@mc.pp.se
State New
Headers show
Series RISC-V big endian support | expand

Commit Message

Marcus Comstedt Feb. 24, 2021, 9:42 p.m. UTC 
gcc/
	* testsuite/gcc.target/riscv/shift-shift-5.c (sub): Change
	order of struct fields depending on byteorder.
---
 gcc/testsuite/gcc.target/riscv/shift-shift-5.c | 4 ++++
 1 file changed, 4 insertions(+)
diff mbox series

Patch

diff --git a/gcc/testsuite/gcc.target/riscv/shift-shift-5.c b/gcc/testsuite/gcc.target/riscv/shift-shift-5.c
index 5b2ae89a471..0ecab9723c9 100644
--- a/gcc/testsuite/gcc.target/riscv/shift-shift-5.c
+++ b/gcc/testsuite/gcc.target/riscv/shift-shift-5.c
@@ -7,7 +7,11 @@  unsigned long
 sub (long l)
 {
   union u {
+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
     struct s { int a : 19; unsigned int b : 13; int x; } s;
+#else
+    struct s { int x; unsigned int b : 13; int a : 19; } s;
+#endif
     long l;
   } u;
   u.l = l;