From patchwork Wed Feb 24 21:42:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marcus Comstedt X-Patchwork-Id: 1444063 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=sourceware.org; envelope-from=gcc-patches-bounces@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; secure) header.d=mc.pp.se header.i=@mc.pp.se header.a=rsa-sha256 header.s=hedgehog header.b=qMQGmT3h; dkim-atps=neutral Received: from sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Dm8YY4pB2z9sSC for ; Thu, 25 Feb 2021 08:43:29 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 57450395543A; Wed, 24 Feb 2021 21:43:13 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from bahamut.mc.pp.se (bahamut.mc.pp.se [IPv6:2001:470:dcd3:1:214:4fff:fe97:7322]) by sourceware.org (Postfix) with ESMTP id 86DEC3955415 for ; Wed, 24 Feb 2021 21:43:10 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 86DEC3955415 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=mc.pp.se Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=marcus@mc.pp.se Received: from hakua (hakua [192.168.42.40]) by bahamut.mc.pp.se (Postfix) with SMTP id 5DED2A39E6; Wed, 24 Feb 2021 22:43:08 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=mc.pp.se; s=hedgehog; t=1614202989; bh=diKS0MutaD6cqdYlPcwXjD+l0bsPXKBnZbuahwXiNwI=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Transfer-Encoding; b=qMQGmT3hCO4yce+tAuwPlstv wicTTgeIPYBIHna3VzCrr/lqO7HE3NYDQctLwsCbPDStv0TjayO63iQTnSfbNWML0wJ 6iFDXuBXTO8bW1F/ijiTdwPri2N6YfqiZk3G7IuD6JbbINPRoaQNDr/MWGmG6yjKWtz vKPW5RRYZ/zFo= Received: by hakua (sSMTP sendmail emulation); Wed, 24 Feb 2021 22:43:08 +0100 From: "Marcus Comstedt" To: gcc-patches@gcc.gnu.org Subject: [PATCH v3 4/6] RISC-V: Fix trampoline generation on big endian Date: Wed, 24 Feb 2021 22:42:58 +0100 Message-Id: <20210224214300.30921-5-marcus@mc.pp.se> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210224214300.30921-1-marcus@mc.pp.se> References: <20210224214300.30921-1-marcus@mc.pp.se> MIME-Version: 1.0 X-Spam-Status: No, score=-13.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marcus Comstedt Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" gcc/ * config/riscv/riscv.c (riscv_swap_instruction): New function to byteswap an SImode rtx containing an instruction. (riscv_trampoline_init): Byteswap the generated instructions when needed. --- gcc/config/riscv/riscv.c | 19 +++++++++++++++---- 1 file changed, 15 insertions(+), 4 deletions(-) diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c index eab14602355..1cd795bd19c 100644 --- a/gcc/config/riscv/riscv.c +++ b/gcc/config/riscv/riscv.c @@ -1073,6 +1073,15 @@ riscv_force_binary (machine_mode mode, enum rtx_code code, rtx x, rtx y) return riscv_emit_binary (code, gen_reg_rtx (mode), x, y); } +static rtx +riscv_swap_instruction (rtx inst) +{ + gcc_assert (GET_MODE (inst) == SImode); + if (BYTES_BIG_ENDIAN) + inst = expand_unop (SImode, bswap_optab, inst, gen_reg_rtx (SImode), 1); + return inst; +} + /* Copy VALUE to a register and return that register. If new pseudos are allowed, copy it into a new register, otherwise use DEST. */ @@ -4953,7 +4962,7 @@ riscv_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value) gen_int_mode (lui_hi_chain_code, SImode)); mem = adjust_address (m_tramp, SImode, 0); - riscv_emit_move (mem, lui_hi_chain); + riscv_emit_move (mem, riscv_swap_instruction (lui_hi_chain)); /* Gen lui t0, hi(func). */ rtx hi_func = riscv_force_binary (SImode, PLUS, target_function, @@ -4965,7 +4974,7 @@ riscv_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value) gen_int_mode (lui_hi_func_code, SImode)); mem = adjust_address (m_tramp, SImode, 1 * GET_MODE_SIZE (SImode)); - riscv_emit_move (mem, lui_hi_func); + riscv_emit_move (mem, riscv_swap_instruction (lui_hi_func)); /* Gen addi t2, t2, lo(chain). */ rtx lo_chain = riscv_force_binary (SImode, AND, chain_value, @@ -4980,7 +4989,7 @@ riscv_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value) force_reg (SImode, GEN_INT (lo_chain_code))); mem = adjust_address (m_tramp, SImode, 2 * GET_MODE_SIZE (SImode)); - riscv_emit_move (mem, addi_lo_chain); + riscv_emit_move (mem, riscv_swap_instruction (addi_lo_chain)); /* Gen jr t0, lo(func). */ rtx lo_func = riscv_force_binary (SImode, AND, target_function, @@ -4993,7 +5002,7 @@ riscv_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value) force_reg (SImode, GEN_INT (lo_func_code))); mem = adjust_address (m_tramp, SImode, 3 * GET_MODE_SIZE (SImode)); - riscv_emit_move (mem, jr_lo_func); + riscv_emit_move (mem, riscv_swap_instruction (jr_lo_func)); } else { @@ -5019,6 +5028,8 @@ riscv_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value) /* Copy the trampoline code. */ for (i = 0; i < ARRAY_SIZE (trampoline); i++) { + if (BYTES_BIG_ENDIAN) + trampoline[i] = __builtin_bswap32(trampoline[i]); mem = adjust_address (m_tramp, SImode, i * GET_MODE_SIZE (SImode)); riscv_emit_move (mem, gen_int_mode (trampoline[i], SImode)); }