From patchwork Wed Feb 10 15:12:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jakub Jelinek X-Patchwork-Id: 1439033 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=sourceware.org; envelope-from=gcc-patches-bounces@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=g7+tyFcs; dkim-atps=neutral Received: from sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DbNZ94ln8z9sB4 for ; Thu, 11 Feb 2021 02:13:33 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 32BDA39960D2; Wed, 10 Feb 2021 15:12:56 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 32BDA39960D2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1612969976; bh=gZpIZR5bYEWZ8G+7cmkL1fT6PRfGWVteT7ArZuKwlLM=; h=Date:To:Subject:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:Cc:From; b=g7+tyFcsgceEbzCzwMmoXWd6xYkrzGKxBWkD8NJ19wS6cpXagm1Qz3DJDt/cCk7o3 +f3LxvvFD+k2LdG8lGILtKLz9LiEcmk/QRXEhRjF1HLmSUW3VNgHlGXw40suGlvR6j KByA/gnqlb2eb9p6WdddGEjzsKoElzrZSHetZQGA= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [63.128.21.124]) by sourceware.org (Postfix) with ESMTP id 251B93857821 for ; Wed, 10 Feb 2021 15:12:53 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 251B93857821 Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-344-NIsc6q0aO4677TUcBBzzYA-1; Wed, 10 Feb 2021 10:12:51 -0500 X-MC-Unique: NIsc6q0aO4677TUcBBzzYA-1 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 1CD78801962; Wed, 10 Feb 2021 15:12:50 +0000 (UTC) Received: from tucnak.zalov.cz (ovpn-112-197.ams2.redhat.com [10.36.112.197]) by smtp.corp.redhat.com (Postfix) with ESMTPS id A0D075D6DC; Wed, 10 Feb 2021 15:12:49 +0000 (UTC) Received: from tucnak.zalov.cz (localhost [127.0.0.1]) by tucnak.zalov.cz (8.16.1/8.16.1) with ESMTPS id 11AFCk871185958 (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384 bits=256 verify=NOT); Wed, 10 Feb 2021 16:12:47 +0100 Received: (from jakub@localhost) by tucnak.zalov.cz (8.16.1/8.16.1/Submit) id 11AFCku81185957; Wed, 10 Feb 2021 16:12:46 +0100 Date: Wed, 10 Feb 2021 16:12:46 +0100 To: Uros Bizjak Subject: [PATCH] i386: Fix ICEs due to simplify_gen_subreg returning NULL [PR99025] Message-ID: <20210210151246.GM4020736@tucnak> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Disposition: inline X-Spam-Status: No, score=-6.4 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H4, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Jakub Jelinek via Gcc-patches From: Jakub Jelinek Reply-To: Jakub Jelinek Cc: gcc-patches@gcc.gnu.org Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" Hi! In these patterns, we call simplify_gen_subreg on the input operand to create paradoxical subregs that have 2x, 4x or 8x elements as the input operand. That works fine if the input operand is a REG, but when it is a SUBREG, RTL doesn't allow SUBREG of SUBREG and so relies on simplify_subreg actually simplifying it. And e.g. if the input operand is a SUBREG that changes the element mode (floating vs. non-floating) and then combined with a paradoxical subreg (i.e. different size) this can easily fail, then simplify_gen_subreg returns NULL but we still use it in instructions. Fixed by forcing the operands into REG. Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk? 2021-02-10 Jakub Jelinek PR target/99025 * config/i386/sse.md (fix_truncv2sfv2di2, v8qiv8hi2, v8qiv8si2, v4qiv4si2, v4hiv4si2, v8qiv8di2, v4qiv4di2, v2qiv2di2, v4hiv4di2, v2hiv2di2, v2siv2di2): Force operands[1] into REG before calling simplify_gen_subreg on it. * gcc.target/i386/pr99025.c: New test. Jakub --- gcc/config/i386/sse.md.jj 2021-02-10 07:52:32.673901634 +0100 +++ gcc/config/i386/sse.md 2021-02-10 10:57:37.229665371 +0100 @@ -6356,6 +6356,7 @@ (define_expand "fix_truncv (match_operand:V2SF 1 "register_operand")))] "TARGET_AVX512DQ && TARGET_AVX512VL" { + operands[1] = force_reg (V2SFmode, operands[1]); operands[1] = simplify_gen_subreg (V4SFmode, operands[1], V2SFmode, 0); emit_insn (gen_avx512dq_fix_truncv2sfv2di2 (operands[0], operands[1])); @@ -18013,6 +18014,7 @@ (define_expand "v8qiv8hi2" { if (!MEM_P (operands[1])) { + operands[1] = force_reg (V8QImode, operands[1]); operands[1] = simplify_gen_subreg (V16QImode, operands[1], V8QImode, 0); emit_insn (gen_sse4_1_v8qiv8hi2 (operands[0], operands[1])); DONE; @@ -18090,6 +18092,7 @@ (define_expand "v8qiv8si2" { if (!MEM_P (operands[1])) { + operands[1] = force_reg (V8QImode, operands[1]); operands[1] = simplify_gen_subreg (V16QImode, operands[1], V8QImode, 0); emit_insn (gen_avx2_v8qiv8si2 (operands[0], operands[1])); DONE; @@ -18153,6 +18156,7 @@ (define_expand "v4qiv4si2" { if (!MEM_P (operands[1])) { + operands[1] = force_reg (V4QImode, operands[1]); operands[1] = simplify_gen_subreg (V16QImode, operands[1], V4QImode, 0); emit_insn (gen_sse4_1_v4qiv4si2 (operands[0], operands[1])); DONE; @@ -18279,6 +18283,7 @@ (define_expand "v4hiv4si2" { if (!MEM_P (operands[1])) { + operands[1] = force_reg (V4HImode, operands[1]); operands[1] = simplify_gen_subreg (V8HImode, operands[1], V4HImode, 0); emit_insn (gen_sse4_1_v4hiv4si2 (operands[0], operands[1])); DONE; @@ -18366,6 +18371,7 @@ (define_expand "v8qiv8di2" { if (!MEM_P (operands[1])) { + operands[1] = force_reg (V8QImode, operands[1]); operands[1] = simplify_gen_subreg (V16QImode, operands[1], V8QImode, 0); emit_insn (gen_avx512f_v8qiv8di2 (operands[0], operands[1])); DONE; @@ -18427,6 +18433,7 @@ (define_expand "v4qiv4di2" { if (!MEM_P (operands[1])) { + operands[1] = force_reg (V8QImode, operands[1]); operands[1] = simplify_gen_subreg (V16QImode, operands[1], V8QImode, 0); emit_insn (gen_avx2_v4qiv4di2 (operands[0], operands[1])); DONE; @@ -18453,6 +18460,7 @@ (define_expand "v2qiv2di2" (match_operand:V2QI 1 "register_operand")))] "TARGET_SSE4_1" { + operands[1] = force_reg (V2QImode, operands[1]); operands[1] = simplify_gen_subreg (V16QImode, operands[1], V2QImode, 0); emit_insn (gen_sse4_1_v2qiv2di2 (operands[0], operands[1])); DONE; @@ -18525,6 +18533,7 @@ (define_expand "v4hiv4di2" { if (!MEM_P (operands[1])) { + operands[1] = force_reg (V4HImode, operands[1]); operands[1] = simplify_gen_subreg (V8HImode, operands[1], V4HImode, 0); emit_insn (gen_avx2_v4hiv4di2 (operands[0], operands[1])); DONE; @@ -18586,6 +18595,7 @@ (define_expand "v2hiv2di2" { if (!MEM_P (operands[1])) { + operands[1] = force_reg (V2HImode, operands[1]); operands[1] = simplify_gen_subreg (V8HImode, operands[1], V2HImode, 0); emit_insn (gen_sse4_1_v2hiv2di2 (operands[0], operands[1])); DONE; @@ -18737,6 +18747,7 @@ (define_expand "v2siv2di2" { if (!MEM_P (operands[1])) { + operands[1] = force_reg (V2SImode, operands[1]); operands[1] = simplify_gen_subreg (V4SImode, operands[1], V2SImode, 0); emit_insn (gen_sse4_1_v2siv2di2 (operands[0], operands[1])); DONE; --- gcc/testsuite/gcc.target/i386/pr99025.c.jj 2021-02-09 19:17:29.705924814 +0100 +++ gcc/testsuite/gcc.target/i386/pr99025.c 2021-02-09 19:17:10.687137688 +0100 @@ -0,0 +1,17 @@ +/* PR target/99025 */ +/* { dg-do compile } */ +/* { dg-options "-O3 -msse4" } */ + +long v[16]; +int w; +union U { float u; int r; } x; + +void +foo (float y) +{ + union U z; + x.u = w; + v[5] = x.r; + z.u = y; + v[6] = z.r; +}