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Wed, 6 Jan 2021 01:54:44 +0000 (GMT) Received: from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id C6D19A405C; Wed, 6 Jan 2021 01:54:43 +0000 (GMT) Received: from localhost.localdomain (unknown [9.145.39.19]) by b06wcsmtp001.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 6 Jan 2021 01:54:43 +0000 (GMT) To: gcc-patches@gcc.gnu.org Subject: [PATCH] Add input_modes parameter to TARGET_MD_ASM_ADJUST hook Date: Wed, 6 Jan 2021 02:54:39 +0100 Message-Id: <20210106015439.1522256-1-iii@linux.ibm.com> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.343, 18.0.737 definitions=2021-01-05_09:2021-01-05, 2021-01-05 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 suspectscore=0 mlxlogscore=999 lowpriorityscore=0 spamscore=0 adultscore=0 malwarescore=0 impostorscore=0 phishscore=0 mlxscore=0 clxscore=1015 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2009150000 definitions=main-2101060006 X-Spam-Status: No, score=-12.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H4, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Ilya Leoshkevich via Gcc-patches From: Ilya Leoshkevich Reply-To: Ilya Leoshkevich Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" Bootstrapped and regtested on x86_64-redhat-linux. I also built cross-compilers for arm-linux-gnueabi, cris-elf mn10300-elf, nds32-linux-gnu, pdp11-aout (didn't fully work due to https://www.mail-archive.com/gcc-patches@gcc.gnu.org/msg251887.html, but the changed code compiled fine), powerpc-linux-gnu, vax-linux-gnu and visium-elf, but didn't test them. I ran into this issue while implementing TARGET_MD_ASM_ADJUST for s390. Ok for master? If TARGET_MD_ASM_ADJUST changes a mode of an input operand (which should be ok as long as the hook itself as well as after_md_seq make up for it), input_mode will contain stale information. It might be tempting to fix this by removing input_mode altogether and just using GET_MODE (), but this will not work correctly with constants. So add input_modes parameter and document that it should be updated whenever inputs parameter is updated. gcc/ChangeLog: 2021-01-05 Ilya Leoshkevich * cfgexpand.c (expand_asm_loc): Pass new parameter. (expand_asm_stmt): Likewise. * config/arm/aarch-common-protos.h (arm_md_asm_adjust): Add new parameter. * config/arm/aarch-common.c (arm_md_asm_adjust): Likewise. * config/arm/arm.c (thumb1_md_asm_adjust): Likewise. * config/cris/cris.c (cris_md_asm_adjust): Likewise. * config/i386/i386.c (ix86_md_asm_adjust): Likewise. * config/mn10300/mn10300.c (mn10300_md_asm_adjust): Likewise. * config/nds32/nds32.c (nds32_md_asm_adjust): Likewise. * config/pdp11/pdp11.c (pdp11_md_asm_adjust): Likewise. * config/rs6000/rs6000.c (rs6000_md_asm_adjust): Likewise. * config/vax/vax.c (vax_md_asm_adjust): Likewise. * config/visium/visium.c (visium_md_asm_adjust): Likewise. * target.def (md_asm_adjust): Likewise. --- gcc/cfgexpand.c | 16 ++++++++-------- gcc/config/arm/aarch-common-protos.h | 8 ++++---- gcc/config/arm/aarch-common.c | 7 ++++--- gcc/config/arm/arm.c | 14 ++++++++------ gcc/config/cris/cris.c | 7 ++++--- gcc/config/i386/i386.c | 7 ++++--- gcc/config/mn10300/mn10300.c | 7 ++++--- gcc/config/nds32/nds32.c | 1 + gcc/config/pdp11/pdp11.c | 9 +++++---- gcc/config/rs6000/rs6000.c | 7 ++++--- gcc/config/vax/vax.c | 3 ++- gcc/config/visium/visium.c | 12 +++++++----- gcc/doc/tm.texi | 10 ++++++---- gcc/target.def | 13 ++++++++----- 14 files changed, 69 insertions(+), 52 deletions(-) diff --git a/gcc/cfgexpand.c b/gcc/cfgexpand.c index b73019b241f..e25528261a0 100644 --- a/gcc/cfgexpand.c +++ b/gcc/cfgexpand.c @@ -2879,6 +2879,7 @@ expand_asm_loc (tree string, int vol, location_t locus) rtx asm_op, clob; unsigned i, nclobbers; auto_vec input_rvec, output_rvec; + auto_vec input_mode; auto_vec constraints; auto_vec clobber_rvec; HARD_REG_SET clobbered_regs; @@ -2888,9 +2889,8 @@ expand_asm_loc (tree string, int vol, location_t locus) clobber_rvec.safe_push (clob); if (targetm.md_asm_adjust) - targetm.md_asm_adjust (output_rvec, input_rvec, - constraints, clobber_rvec, - clobbered_regs); + targetm.md_asm_adjust (output_rvec, input_rvec, input_mode, + constraints, clobber_rvec, clobbered_regs); asm_op = body; nclobbers = clobber_rvec.length (); @@ -3067,8 +3067,8 @@ expand_asm_stmt (gasm *stmt) return; } - /* There are some legacy diagnostics in here, and also avoids a - sixth parameger to targetm.md_asm_adjust. */ + /* There are some legacy diagnostics in here, and also avoids an extra + parameter to targetm.md_asm_adjust. */ save_input_location s_i_l(locus); unsigned noutputs = gimple_asm_noutputs (stmt); @@ -3419,9 +3419,9 @@ expand_asm_stmt (gasm *stmt) the flags register. */ rtx_insn *after_md_seq = NULL; if (targetm.md_asm_adjust) - after_md_seq = targetm.md_asm_adjust (output_rvec, input_rvec, - constraints, clobber_rvec, - clobbered_regs); + after_md_seq + = targetm.md_asm_adjust (output_rvec, input_rvec, input_mode, + constraints, clobber_rvec, clobbered_regs); /* Do not allow the hook to change the output and input count, lest it mess up the operand numbering. */ diff --git a/gcc/config/arm/aarch-common-protos.h b/gcc/config/arm/aarch-common-protos.h index 251de3d61a8..cbef50dde71 100644 --- a/gcc/config/arm/aarch-common-protos.h +++ b/gcc/config/arm/aarch-common-protos.h @@ -143,9 +143,9 @@ struct cpu_cost_table const struct vector_cost_table vect; }; -rtx_insn * -arm_md_asm_adjust (vec &outputs, vec &/*inputs*/, - vec &constraints, - vec &clobbers, HARD_REG_SET &clobbered_regs); +rtx_insn *arm_md_asm_adjust (vec &outputs, vec & /*inputs*/, + vec & /*input_modes*/, + vec &constraints, + vec &clobbers, HARD_REG_SET &clobbered_regs); #endif /* GCC_AARCH_COMMON_PROTOS_H */ diff --git a/gcc/config/arm/aarch-common.c b/gcc/config/arm/aarch-common.c index 6ff4215921d..24711d5b4f7 100644 --- a/gcc/config/arm/aarch-common.c +++ b/gcc/config/arm/aarch-common.c @@ -531,9 +531,10 @@ arm_mac_accumulator_is_mul_result (rtx producer, rtx consumer) We implement asm flag outputs. */ rtx_insn * -arm_md_asm_adjust (vec &outputs, vec &/*inputs*/, - vec &constraints, - vec &/*clobbers*/, HARD_REG_SET &/*clobbered_regs*/) +arm_md_asm_adjust (vec &outputs, vec & /*inputs*/, + vec & /*input_modes*/, + vec &constraints, vec & /*clobbers*/, + HARD_REG_SET & /*clobbered_regs*/) { bool saw_asm_flag = false; diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index c8e25714386..ffd34fe3f66 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -328,9 +328,10 @@ static unsigned int arm_hard_regno_nregs (unsigned int, machine_mode); static bool arm_hard_regno_mode_ok (unsigned int, machine_mode); static bool arm_modes_tieable_p (machine_mode, machine_mode); static HOST_WIDE_INT arm_constant_alignment (const_tree, HOST_WIDE_INT); -static rtx_insn * thumb1_md_asm_adjust (vec &, vec &, - vec &, vec &, - HARD_REG_SET &); +static rtx_insn *thumb1_md_asm_adjust (vec &, vec &, + vec &, + vec &, vec &, + HARD_REG_SET &); /* Table of machine attributes. */ static const struct attribute_spec arm_attribute_table[] = @@ -33887,9 +33888,10 @@ arm_run_selftests (void) Unlike the arm version, we do NOT implement asm flag outputs. */ rtx_insn * -thumb1_md_asm_adjust (vec &outputs, vec &/*inputs*/, - vec &constraints, - vec &/*clobbers*/, HARD_REG_SET &/*clobbered_regs*/) +thumb1_md_asm_adjust (vec &outputs, vec & /*inputs*/, + vec & /*input_modes*/, + vec &constraints, vec & /*clobbers*/, + HARD_REG_SET & /*clobbered_regs*/) { for (unsigned i = 0, n = outputs.length (); i < n; ++i) if (strncmp (constraints[i], "=@cc", 4) == 0) diff --git a/gcc/config/cris/cris.c b/gcc/config/cris/cris.c index 48ea8552e59..5cae2192fae 100644 --- a/gcc/config/cris/cris.c +++ b/gcc/config/cris/cris.c @@ -150,7 +150,7 @@ static rtx cris_function_incoming_arg (cumulative_args_t, static void cris_function_arg_advance (cumulative_args_t, const function_arg_info &); static rtx_insn *cris_md_asm_adjust (vec &, vec &, - vec &, + vec &, vec &, vec &, HARD_REG_SET &); static void cris_option_override (void); @@ -3489,8 +3489,9 @@ cris_function_arg_advance (cumulative_args_t ca_v, static rtx_insn * cris_md_asm_adjust (vec &outputs, vec &inputs, - vec &constraints, - vec &clobbers, HARD_REG_SET &clobbered_regs) + vec & /*input_modes*/, + vec &constraints, vec &clobbers, + HARD_REG_SET &clobbered_regs) { /* For the time being, all asms clobber condition codes. Revisit when there's a reasonable use for inputs/outputs diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index fad50e7e537..3e93e5210d9 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -21396,9 +21396,10 @@ ix86_c_mode_for_suffix (char suffix) with the old cc0-based compiler. */ static rtx_insn * -ix86_md_asm_adjust (vec &outputs, vec &/*inputs*/, - vec &constraints, - vec &clobbers, HARD_REG_SET &clobbered_regs) +ix86_md_asm_adjust (vec &outputs, vec & /*inputs*/, + vec & /*input_modes*/, + vec &constraints, vec &clobbers, + HARD_REG_SET &clobbered_regs) { bool saw_asm_flag = false; diff --git a/gcc/config/mn10300/mn10300.c b/gcc/config/mn10300/mn10300.c index bdacade468a..c1c2e6e3b5c 100644 --- a/gcc/config/mn10300/mn10300.c +++ b/gcc/config/mn10300/mn10300.c @@ -2847,9 +2847,10 @@ mn10300_conditional_register_usage (void) with the old cc0-based compiler. */ static rtx_insn * -mn10300_md_asm_adjust (vec &/*outputs*/, vec &/*inputs*/, - vec &/*constraints*/, - vec &clobbers, HARD_REG_SET &clobbered_regs) +mn10300_md_asm_adjust (vec & /*outputs*/, vec & /*inputs*/, + vec & /*input_modes*/, + vec & /*constraints*/, vec &clobbers, + HARD_REG_SET &clobbered_regs) { clobbers.safe_push (gen_rtx_REG (CCmode, CC_REG)); SET_HARD_REG_BIT (clobbered_regs, CC_REG); diff --git a/gcc/config/nds32/nds32.c b/gcc/config/nds32/nds32.c index 226da0b8859..7217d7879b6 100644 --- a/gcc/config/nds32/nds32.c +++ b/gcc/config/nds32/nds32.c @@ -4197,6 +4197,7 @@ nds32_option_override (void) static rtx_insn * nds32_md_asm_adjust (vec &outputs ATTRIBUTE_UNUSED, vec &inputs ATTRIBUTE_UNUSED, + vec &input_modes ATTRIBUTE_UNUSED, vec &constraints ATTRIBUTE_UNUSED, vec &clobbers, HARD_REG_SET &clobbered_regs) { diff --git a/gcc/config/pdp11/pdp11.c b/gcc/config/pdp11/pdp11.c index bd6e0dc771b..eb3bea497bf 100644 --- a/gcc/config/pdp11/pdp11.c +++ b/gcc/config/pdp11/pdp11.c @@ -155,7 +155,7 @@ static bool pdp11_rtx_costs (rtx, machine_mode, int, int, int *, bool); static int pdp11_addr_cost (rtx, machine_mode, addr_space_t, bool); static int pdp11_insn_cost (rtx_insn *insn, bool speed); static rtx_insn *pdp11_md_asm_adjust (vec &, vec &, - vec &, + vec &, vec &, vec &, HARD_REG_SET &); static bool pdp11_return_in_memory (const_tree, const_tree); static rtx pdp11_function_value (const_tree, const_tree, bool); @@ -2139,9 +2139,10 @@ pdp11_cmp_length (rtx *operands, int words) compiler. */ static rtx_insn * -pdp11_md_asm_adjust (vec &/*outputs*/, vec &/*inputs*/, - vec &/*constraints*/, - vec &clobbers, HARD_REG_SET &clobbered_regs) +pdp11_md_asm_adjust (vec & /*outputs*/, vec & /*inputs*/, + vec & /*input_modes*/, + vec & /*constraints*/, vec &clobbers, + HARD_REG_SET &clobbered_regs) { clobbers.safe_push (gen_rtx_REG (CCmode, CC_REGNUM)); SET_HARD_REG_BIT (clobbered_regs, CC_REGNUM); diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 67681d18150..3494160c9ef 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -3410,9 +3410,10 @@ rs6000_builtin_mask_calculate (void) not such a great idea. */ static rtx_insn * -rs6000_md_asm_adjust (vec &/*outputs*/, vec &/*inputs*/, - vec &/*constraints*/, - vec &clobbers, HARD_REG_SET &clobbered_regs) +rs6000_md_asm_adjust (vec & /*outputs*/, vec & /*inputs*/, + vec & /*input_modes*/, + vec & /*constraints*/, vec &clobbers, + HARD_REG_SET &clobbered_regs) { clobbers.safe_push (gen_rtx_REG (SImode, CA_REGNO)); SET_HARD_REG_BIT (clobbered_regs, CA_REGNO); diff --git a/gcc/config/vax/vax.c b/gcc/config/vax/vax.c index fe4c14e9998..726c3719138 100644 --- a/gcc/config/vax/vax.c +++ b/gcc/config/vax/vax.c @@ -56,7 +56,7 @@ static int vax_address_cost (rtx, machine_mode, addr_space_t, bool); static bool vax_rtx_costs (rtx, machine_mode, int, int, int *, bool); static machine_mode vax_cc_modes_compatible (machine_mode, machine_mode); static rtx_insn *vax_md_asm_adjust (vec &, vec &, - vec &, + vec &, vec &, vec &, HARD_REG_SET &); static rtx vax_function_arg (cumulative_args_t, const function_arg_info &); static void vax_function_arg_advance (cumulative_args_t, @@ -1174,6 +1174,7 @@ vax_cc_modes_compatible (machine_mode m1, machine_mode m2) static rtx_insn * vax_md_asm_adjust (vec &outputs ATTRIBUTE_UNUSED, vec &inputs ATTRIBUTE_UNUSED, + vec &input_modes ATTRIBUTE_UNUSED, vec &constraints ATTRIBUTE_UNUSED, vec &clobbers, HARD_REG_SET &clobbered_regs) { diff --git a/gcc/config/visium/visium.c b/gcc/config/visium/visium.c index e0b88be45bb..7eb22485297 100644 --- a/gcc/config/visium/visium.c +++ b/gcc/config/visium/visium.c @@ -188,8 +188,9 @@ static bool visium_frame_pointer_required (void); static tree visium_build_builtin_va_list (void); static rtx_insn *visium_md_asm_adjust (vec &, vec &, - vec &, - vec &, HARD_REG_SET &); + vec &, + vec &, vec &, + HARD_REG_SET &); static bool visium_legitimate_constant_p (machine_mode, rtx); @@ -791,9 +792,10 @@ visium_conditional_register_usage (void) the original cc0-based compiler. */ static rtx_insn * -visium_md_asm_adjust (vec &/*outputs*/, vec &/*inputs*/, - vec &/*constraints*/, - vec &clobbers, HARD_REG_SET &clobbered_regs) +visium_md_asm_adjust (vec & /*outputs*/, vec & /*inputs*/, + vec & /*input_modes*/, + vec & /*constraints*/, vec &clobbers, + HARD_REG_SET &clobbered_regs) { clobbers.safe_push (gen_rtx_REG (CCmode, FLAGS_REGNUM)); SET_HARD_REG_BIT (clobbered_regs, FLAGS_REGNUM); diff --git a/gcc/doc/tm.texi b/gcc/doc/tm.texi index 062785af1e2..d5a090f0a75 100644 --- a/gcc/doc/tm.texi +++ b/gcc/doc/tm.texi @@ -11487,15 +11487,17 @@ from shared libraries (DLLs). You need not define this macro if it would always evaluate to zero. @end defmac -@deftypefn {Target Hook} {rtx_insn *} TARGET_MD_ASM_ADJUST (vec& @var{outputs}, vec& @var{inputs}, vec& @var{constraints}, vec& @var{clobbers}, HARD_REG_SET& @var{clobbered_regs}) +@deftypefn {Target Hook} {rtx_insn *} TARGET_MD_ASM_ADJUST (vec& @var{outputs}, vec& @var{inputs}, vec& @var{input_modes}, vec& @var{constraints}, vec& @var{clobbers}, HARD_REG_SET& @var{clobbered_regs}) This target hook may add @dfn{clobbers} to @var{clobbers} and @var{clobbered_regs} for any hard regs the port wishes to automatically clobber for an asm. The @var{outputs} and @var{inputs} may be inspected to avoid clobbering a register that is already used by the asm. -It may modify the @var{outputs}, @var{inputs}, and @var{constraints} -as necessary for other pre-processing. In this case the return value is -a sequence of insns to emit after the asm. +It may modify the @var{outputs}, @var{inputs}, @var{input_modes}, and +@var{constraints} as necessary for other pre-processing. In this case the +return value is a sequence of insns to emit after the asm. Note that +changes to @var{inputs} must be accompanied by the corresponding changes +to @var{input_modes}. @end deftypefn @defmac MATH_LIBRARY diff --git a/gcc/target.def b/gcc/target.def index be7fcde961a..73506d9020c 100644 --- a/gcc/target.def +++ b/gcc/target.def @@ -4158,12 +4158,15 @@ DEFHOOK clobber for an asm. The @var{outputs} and @var{inputs} may be inspected\n\ to avoid clobbering a register that is already used by the asm.\n\ \n\ -It may modify the @var{outputs}, @var{inputs}, and @var{constraints}\n\ -as necessary for other pre-processing. In this case the return value is\n\ -a sequence of insns to emit after the asm.", +It may modify the @var{outputs}, @var{inputs}, @var{input_modes}, and\n\ +@var{constraints} as necessary for other pre-processing. In this case the\n\ +return value is a sequence of insns to emit after the asm. Note that\n\ +changes to @var{inputs} must be accompanied by the corresponding changes\n\ +to @var{input_modes}.", rtx_insn *, - (vec& outputs, vec& inputs, vec& constraints, - vec& clobbers, HARD_REG_SET& clobbered_regs), + (vec& outputs, vec& inputs, vec& input_modes, + vec& constraints, vec& clobbers, + HARD_REG_SET& clobbered_regs), NULL) /* This target hook allows the backend to specify a calling convention