diff mbox series

[committed,6/6] arc: generate mac(u) insn instead of macd(u) when destination is accl

Message ID 20201229113655.3761444-6-claziss@synopsys.com
State New
Headers show
Series [committed,1/6] arc: Don't use predicated vadd2 instructions in mov patterns. | expand

Commit Message

Claudiu Zissulescu Ianculescu Dec. 29, 2020, 11:36 a.m. UTC 
Generate MAC(U) instruction instead of MACD(U) when the destination
register is already choosen as ACCL register.

gcc/
2020-12-29  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/arc/arc.md (maddsidi4_split): Skip macd gen, use mac insn
	instead.
	(macd): Update register letters.
	(umaddsidi4_split): Skip macdu gen, use macu insn instead.
	(macdu): Update register letters.

Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
---
 gcc/config/arc/arc.md | 24 ++++++++++++++----------
 1 file changed, 14 insertions(+), 10 deletions(-)
diff mbox series

Patch

diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
index 75c32f6d3e9..b616c7fb82c 100644
--- a/gcc/config/arc/arc.md
+++ b/gcc/config/arc/arc.md
@@ -6176,12 +6176,14 @@  (define_insn_and_split "maddsidi4_split"
   "{
    rtx acc_reg = gen_rtx_REG (DImode, ACC_REG_FIRST);
    emit_move_insn (acc_reg, operands[3]);
-   if (TARGET_PLUS_MACD && even_register_operand (operands[0], DImode))
-     emit_insn (gen_macd (operands[0], operands[1], operands[2]));
+   if (TARGET_PLUS_MACD && even_register_operand (operands[0], DImode)
+       && REGNO (operands[0]) != ACCL_REGNO)
+      emit_insn (gen_macd (operands[0], operands[1], operands[2]));
    else
      {
       emit_insn (gen_mac (operands[1], operands[2]));
-      emit_move_insn (operands[0], acc_reg);
+      if (REGNO (operands[0]) != ACCL_REGNO)
+        emit_move_insn (operands[0], acc_reg);
      }
    DONE;
    }"
@@ -6192,8 +6194,8 @@  (define_insn "macd"
   [(set (match_operand:DI 0 "even_register_operand"	       "=Rcr,r,r")
 	(plus:DI
 	 (mult:DI
-	  (sign_extend:DI (match_operand:SI 1 "register_operand" "%0,c,c"))
-	  (sign_extend:DI (match_operand:SI 2 "extend_operand" " c,cI,Cal")))
+	  (sign_extend:DI (match_operand:SI 1 "register_operand" "%0,r,r"))
+	  (sign_extend:DI (match_operand:SI 2 "extend_operand"    "r,rI,Cal")))
 	 (reg:DI ARCV2_ACC)))
    (set (reg:DI ARCV2_ACC)
 	(plus:DI
@@ -6276,12 +6278,14 @@  (define_insn_and_split "umaddsidi4_split"
   "{
    rtx acc_reg = gen_rtx_REG (DImode, ACC_REG_FIRST);
    emit_move_insn (acc_reg, operands[3]);
-   if (TARGET_PLUS_MACD && even_register_operand (operands[0], DImode))
-     emit_insn (gen_macdu (operands[0], operands[1], operands[2]));
+   if (TARGET_PLUS_MACD && even_register_operand (operands[0], DImode)
+       && REGNO (operands[0]) != ACCL_REGNO)
+      emit_insn (gen_macdu (operands[0], operands[1], operands[2]));
    else
      {
       emit_insn (gen_macu (operands[1], operands[2]));
-      emit_move_insn (operands[0], acc_reg);
+      if (REGNO (operands[0]) != ACCL_REGNO)
+        emit_move_insn (operands[0], acc_reg);
      }
    DONE;
    }"
@@ -6292,8 +6296,8 @@  (define_insn "macdu"
   [(set (match_operand:DI 0 "even_register_operand"	       "=Rcr,r,r")
 	(plus:DI
 	 (mult:DI
-	  (zero_extend:DI (match_operand:SI 1 "register_operand" "%0,c,c"))
-	  (zero_extend:DI (match_operand:SI 2 "extend_operand" " c,cI,i")))
+	  (zero_extend:DI (match_operand:SI 1 "register_operand" "%0,r,r"))
+	  (zero_extend:DI (match_operand:SI 2 "extend_operand"    "r,rI,i")))
 	 (reg:DI ARCV2_ACC)))
    (set (reg:DI ARCV2_ACC)
 	(plus:DI