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Thu, 12 Nov 2020 12:23:15 +0000 (GMT) Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 5D9C811C050; Thu, 12 Nov 2020 12:23:07 +0000 (GMT) Received: from m8345017.lnxne.boe (unknown [9.152.108.100]) by d06av25.portsmouth.uk.ibm.com (Postfix) with ESMTP; Thu, 12 Nov 2020 12:23:07 +0000 (GMT) To: krebbel@linux.ibm.com, gcc-patches@gcc.gnu.org Subject: [PATCH] IBM Z: Define vec_vfees instruction pattern Date: Thu, 12 Nov 2020 13:21:42 +0100 Message-Id: <20201112122141.3263973-1-stefansf@linux.ibm.com> X-Mailer: git-send-email 2.28.0 MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.312, 18.0.737 definitions=2020-11-12_05:2020-11-12, 2020-11-12 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 mlxscore=0 suspectscore=0 priorityscore=1501 adultscore=0 lowpriorityscore=0 malwarescore=0 spamscore=0 phishscore=0 bulkscore=0 clxscore=1015 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2009150000 definitions=main-2011120069 X-Spam-Status: No, score=-8.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Stefan Schulze Frielinghaus via Gcc-patches From: Stefan Schulze Frielinghaus Reply-To: Stefan Schulze Frielinghaus Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" Bootstrapped and regtested on IBM Z. Ok for master? gcc/ChangeLog: * config/s390/vector.md ("vec_vfees"): New insn pattern. --- gcc/config/s390/vector.md | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/gcc/config/s390/vector.md b/gcc/config/s390/vector.md index 31d323930b2..4333a2191ae 100644 --- a/gcc/config/s390/vector.md +++ b/gcc/config/s390/vector.md @@ -1798,6 +1798,32 @@ "vll\t%v0,%1,%2" [(set_attr "op_type" "VRS")]) +; vfeebs, vfeehs, vfeefs +; vfeezbs, vfeezhs, vfeezfs +(define_insn "vec_vfees" + [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v") + (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "v") + (match_operand:VI_HW_QHS 2 "register_operand" "v") + (match_operand:QI 3 "const_mask_operand" "C")] + UNSPEC_VEC_VFEE)) + (set (reg:CCRAW CC_REGNUM) + (unspec:CCRAW [(match_dup 1) + (match_dup 2) + (match_dup 3)] + UNSPEC_VEC_VFEECC))] + "TARGET_VX" +{ + unsigned HOST_WIDE_INT flags = UINTVAL (operands[3]); + + gcc_assert (!(flags & ~(VSTRING_FLAG_ZS | VSTRING_FLAG_CS))); + flags &= ~VSTRING_FLAG_CS; + + if (flags == VSTRING_FLAG_ZS) + return "vfeezs\t%v0,%v1,%v2"; + return "vfees\t%v0,%v1,%v2"; +} + [(set_attr "op_type" "VRR")]) + ; vfenebs, vfenehs, vfenefs ; vfenezbs, vfenezhs, vfenezfs (define_insn "vec_vfenes"