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Asan changes for RISC-V.

Message ID 20201028235817.17405-1-jimw@sifive.com
State New
Headers show
Series Asan changes for RISC-V. | expand

Commit Message

Jim Wilson Oct. 28, 2020, 11:58 p.m. UTC 
We have only riscv64 asan support, there is no riscv32 support as yet.  So I
need to be able to conditionally enable asan support for the riscv target.  I
implemented this by returning zero from the asan_shadow_offset function.  This
requires a change to toplev.c and docs in target.def.

The asan support works on a 5.5 kernel, but does not work on a 4.15 kernel.
The problem is that the asan high memory region is a small wedge below
0x4000000000.  The new kernel puts shared libraries at 0x3fffffffff and going
down which works.  But the old kernel puts shared libraries at 0x2000000000
and going up which does not work, as it isn't in any recognized memory
region.  This might be fixable with more asan work, but we don't really need
support for old kernel versions.

The asan port is curious in that it uses 1<<29 for the shadow offset, but all
other 64-bit targets use a number larger than 1<<32.  But what we have is
working OK for now.

I did a make check RUNTESTFLAGS="asan.exp" on Fedora rawhide image running on
qemu and the results look reasonable.

		=== gcc Summary ===

# of expected passes		1905
# of unexpected failures	11
# of unsupported tests		224

		=== g++ Summary ===

# of expected passes		2002
# of unexpected failures	6
# of unresolved testcases	1
# of unsupported tests		175

OK?

Jim

2020-10-28  Jim Wilson  <jimw@sifive.com>

	gcc/
	* config/riscv/riscv.c (riscv_asan_shadow_offset): New.
	(TARGET_ASAN_SHADOW_OFFSET): New.
	* doc/tm.texi: Regenerated.
	* target.def (asan_shadow_offset); Mention that it can return zero.
	* toplev.c (process_options): Check for and handle zero return from
	targetm.asan_shadow_offset call.

Co-Authored-By: cooper.joshua <cooper.joshua@linux.alibaba.com>
---
 gcc/config/riscv/riscv.c | 16 ++++++++++++++++
 gcc/doc/tm.texi          |  3 ++-
 gcc/target.def           |  3 ++-
 gcc/toplev.c             |  3 ++-
 4 files changed, 22 insertions(+), 3 deletions(-)

Comments

Jim Wilson Nov. 4, 2020, 8:10 p.m. UTC | #1 
On Wed, Oct 28, 2020 at 4:59 PM Jim Wilson <jimw@sifive.com> wrote:

> We have only riscv64 asan support, there is no riscv32 support as yet.  So
> I
> need to be able to conditionally enable asan support for the riscv
> target.  I
> implemented this by returning zero from the asan_shadow_offset function.
> This
> requires a change to toplev.c and docs in target.def.
>
> The asan support works on a 5.5 kernel, but does not work on a 4.15 kernel.
> The problem is that the asan high memory region is a small wedge below
> 0x4000000000.  The new kernel puts shared libraries at 0x3fffffffff and
> going
> down which works.  But the old kernel puts shared libraries at 0x2000000000
> and going up which does not work, as it isn't in any recognized memory
> region.  This might be fixable with more asan work, but we don't really
> need
> support for old kernel versions.
>
> The asan port is curious in that it uses 1<<29 for the shadow offset, but
> all
> other 64-bit targets use a number larger than 1<<32.  But what we have is
> working OK for now.
>
> I did a make check RUNTESTFLAGS="asan.exp" on Fedora rawhide image running
> on
> qemu and the results look reasonable.
>
>                 === gcc Summary ===
>
> # of expected passes            1905
> # of unexpected failures        11
> # of unsupported tests          224
>
>                 === g++ Summary ===
>
> # of expected passes            2002
> # of unexpected failures        6
> # of unresolved testcases       1
> # of unsupported tests          175
>
> OK?
>
> Jim
>
> 2020-10-28  Jim Wilson  <jimw@sifive.com>
>
>         gcc/
>         * config/riscv/riscv.c (riscv_asan_shadow_offset): New.
>         (TARGET_ASAN_SHADOW_OFFSET): New.
>         * doc/tm.texi: Regenerated.
>         * target.def (asan_shadow_offset); Mention that it can return zero.
>         * toplev.c (process_options): Check for and handle zero return from
>         targetm.asan_shadow_offset call.
>
> Co-Authored-By: cooper.joshua <cooper.joshua@linux.alibaba.com>
> ---
>  gcc/config/riscv/riscv.c | 16 ++++++++++++++++
>  gcc/doc/tm.texi          |  3 ++-
>  gcc/target.def           |  3 ++-
>  gcc/toplev.c             |  3 ++-
>  4 files changed, 22 insertions(+), 3 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c
> index 989a9f15250..6909e200de1 100644
> --- a/gcc/config/riscv/riscv.c
> +++ b/gcc/config/riscv/riscv.c
> @@ -5299,6 +5299,19 @@ riscv_gpr_save_operation_p (rtx op)
>    return true;
>  }
>
> +/* Implement TARGET_ASAN_SHADOW_OFFSET.  */
> +
> +static unsigned HOST_WIDE_INT
> +riscv_asan_shadow_offset (void)
> +{
> +  /* We only have libsanitizer support for RV64 at present.
> +
> +     This number must match kRiscv*_ShadowOffset* in the file
> +     libsanitizer/asan/asan_mapping.h which is currently 1<<29 for rv64,
> +     even though 1<<36 makes more sense.  */
> +  return TARGET_64BIT ? (HOST_WIDE_INT_1 << 29) : 0;
> +}
> +
>  /* Initialize the GCC target structure.  */
>  #undef TARGET_ASM_ALIGNED_HI_OP
>  #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
> @@ -5482,6 +5495,9 @@ riscv_gpr_save_operation_p (rtx op)
>  #undef TARGET_NEW_ADDRESS_PROFITABLE_P
>  #define TARGET_NEW_ADDRESS_PROFITABLE_P riscv_new_address_profitable_p
>
> +#undef TARGET_ASAN_SHADOW_OFFSET
> +#define TARGET_ASAN_SHADOW_OFFSET riscv_asan_shadow_offset
> +
>  struct gcc_target targetm = TARGET_INITIALIZER;
>
>  #include "gt-riscv.h"
> diff --git a/gcc/doc/tm.texi b/gcc/doc/tm.texi
> index 24c37f655c8..39c596b647a 100644
> --- a/gcc/doc/tm.texi
> +++ b/gcc/doc/tm.texi
> @@ -12078,7 +12078,8 @@ is zero, which disables this optimization.
>  @deftypefn {Target Hook} {unsigned HOST_WIDE_INT}
> TARGET_ASAN_SHADOW_OFFSET (void)
>  Return the offset bitwise ored into shifted address to get corresponding
>  Address Sanitizer shadow memory address.  NULL if Address Sanitizer is not
> -supported by the target.
> +supported by the target.  May return 0 if Address Sanitizer is not
> supported
> +by a subtarget.
>  @end deftypefn
>
>  @deftypefn {Target Hook} {unsigned HOST_WIDE_INT} TARGET_MEMMODEL_CHECK
> (unsigned HOST_WIDE_INT @var{val})
> diff --git a/gcc/target.def b/gcc/target.def
> index ed2da154e30..268b56b6ebd 100644
> --- a/gcc/target.def
> +++ b/gcc/target.def
> @@ -4452,7 +4452,8 @@ DEFHOOK
>  (asan_shadow_offset,
>   "Return the offset bitwise ored into shifted address to get
> corresponding\n\
>  Address Sanitizer shadow memory address.  NULL if Address Sanitizer is
> not\n\
> -supported by the target.",
> +supported by the target.  May return 0 if Address Sanitizer is not
> supported\n\
> +by a subtarget.",
>   unsigned HOST_WIDE_INT, (void),
>   NULL)
>
> diff --git a/gcc/toplev.c b/gcc/toplev.c
> index 20e231f4d2a..cf89598252c 100644
> --- a/gcc/toplev.c
> +++ b/gcc/toplev.c
> @@ -1834,7 +1834,8 @@ process_options (void)
>      }
>
>    if ((flag_sanitize & SANITIZE_USER_ADDRESS)
> -      && targetm.asan_shadow_offset == NULL)
> +      && ((targetm.asan_shadow_offset == NULL)
> +         || (targetm.asan_shadow_offset () == 0)))
>      {
>        warning_at (UNKNOWN_LOCATION, 0,
>                   "%<-fsanitize=address%> not supported for this target");
> --
> 2.17.1
>
>
Kito Cheng Nov. 6, 2020, 8:05 a.m. UTC | #2 
LGTM.

Verified with Fedora rawhide image running on qemu, kernel version is 5.5.0,
I got slightly different gcc testsuite result, but after reviewing all
failed cases,
it should not be a blocker for this patch.

It  seems environment issue, some minor issues like stack
unwinding or library search path.
e.g
- ld complain cannot find -latomic
- Stack unwinding result not show main in asan report.

                === gcc Summary ===

# of expected passes            2672
# of unexpected failures        25
# of unresolved testcases       14
# of unsupported tests          224
                === g++ Summary ===

# of expected passes            1967
# of unexpected failures        20
# of unresolved testcases       15
# of unsupported tests          175




On Thu, Nov 5, 2020 at 4:11 AM Jim Wilson <jimw@sifive.com> wrote:
>
> On Wed, Oct 28, 2020 at 4:59 PM Jim Wilson <jimw@sifive.com> wrote:
>
> > We have only riscv64 asan support, there is no riscv32 support as yet.  So
> > I
> > need to be able to conditionally enable asan support for the riscv
> > target.  I
> > implemented this by returning zero from the asan_shadow_offset function.
> > This
> > requires a change to toplev.c and docs in target.def.
> >
> > The asan support works on a 5.5 kernel, but does not work on a 4.15 kernel.
> > The problem is that the asan high memory region is a small wedge below
> > 0x4000000000.  The new kernel puts shared libraries at 0x3fffffffff and
> > going
> > down which works.  But the old kernel puts shared libraries at 0x2000000000
> > and going up which does not work, as it isn't in any recognized memory
> > region.  This might be fixable with more asan work, but we don't really
> > need
> > support for old kernel versions.
> >
> > The asan port is curious in that it uses 1<<29 for the shadow offset, but
> > all
> > other 64-bit targets use a number larger than 1<<32.  But what we have is
> > working OK for now.
> >
> > I did a make check RUNTESTFLAGS="asan.exp" on Fedora rawhide image running
> > on
> > qemu and the results look reasonable.
> >
> >                 === gcc Summary ===
> >
> > # of expected passes            1905
> > # of unexpected failures        11
> > # of unsupported tests          224
> >
> >                 === g++ Summary ===
> >
> > # of expected passes            2002
> > # of unexpected failures        6
> > # of unresolved testcases       1
> > # of unsupported tests          175
> >
> > OK?
> >
> > Jim
> >
> > 2020-10-28  Jim Wilson  <jimw@sifive.com>
> >
> >         gcc/
> >         * config/riscv/riscv.c (riscv_asan_shadow_offset): New.
> >         (TARGET_ASAN_SHADOW_OFFSET): New.
> >         * doc/tm.texi: Regenerated.
> >         * target.def (asan_shadow_offset); Mention that it can return zero.
> >         * toplev.c (process_options): Check for and handle zero return from
> >         targetm.asan_shadow_offset call.
> >
> > Co-Authored-By: cooper.joshua <cooper.joshua@linux.alibaba.com>
> > ---
> >  gcc/config/riscv/riscv.c | 16 ++++++++++++++++
> >  gcc/doc/tm.texi          |  3 ++-
> >  gcc/target.def           |  3 ++-
> >  gcc/toplev.c             |  3 ++-
> >  4 files changed, 22 insertions(+), 3 deletions(-)
> >
> > diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c
> > index 989a9f15250..6909e200de1 100644
> > --- a/gcc/config/riscv/riscv.c
> > +++ b/gcc/config/riscv/riscv.c
> > @@ -5299,6 +5299,19 @@ riscv_gpr_save_operation_p (rtx op)
> >    return true;
> >  }
> >
> > +/* Implement TARGET_ASAN_SHADOW_OFFSET.  */
> > +
> > +static unsigned HOST_WIDE_INT
> > +riscv_asan_shadow_offset (void)
> > +{
> > +  /* We only have libsanitizer support for RV64 at present.
> > +
> > +     This number must match kRiscv*_ShadowOffset* in the file
> > +     libsanitizer/asan/asan_mapping.h which is currently 1<<29 for rv64,
> > +     even though 1<<36 makes more sense.  */
> > +  return TARGET_64BIT ? (HOST_WIDE_INT_1 << 29) : 0;
> > +}
> > +
> >  /* Initialize the GCC target structure.  */
> >  #undef TARGET_ASM_ALIGNED_HI_OP
> >  #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
> > @@ -5482,6 +5495,9 @@ riscv_gpr_save_operation_p (rtx op)
> >  #undef TARGET_NEW_ADDRESS_PROFITABLE_P
> >  #define TARGET_NEW_ADDRESS_PROFITABLE_P riscv_new_address_profitable_p
> >
> > +#undef TARGET_ASAN_SHADOW_OFFSET
> > +#define TARGET_ASAN_SHADOW_OFFSET riscv_asan_shadow_offset
> > +
> >  struct gcc_target targetm = TARGET_INITIALIZER;
> >
> >  #include "gt-riscv.h"
> > diff --git a/gcc/doc/tm.texi b/gcc/doc/tm.texi
> > index 24c37f655c8..39c596b647a 100644
> > --- a/gcc/doc/tm.texi
> > +++ b/gcc/doc/tm.texi
> > @@ -12078,7 +12078,8 @@ is zero, which disables this optimization.
> >  @deftypefn {Target Hook} {unsigned HOST_WIDE_INT}
> > TARGET_ASAN_SHADOW_OFFSET (void)
> >  Return the offset bitwise ored into shifted address to get corresponding
> >  Address Sanitizer shadow memory address.  NULL if Address Sanitizer is not
> > -supported by the target.
> > +supported by the target.  May return 0 if Address Sanitizer is not
> > supported
> > +by a subtarget.
> >  @end deftypefn
> >
> >  @deftypefn {Target Hook} {unsigned HOST_WIDE_INT} TARGET_MEMMODEL_CHECK
> > (unsigned HOST_WIDE_INT @var{val})
> > diff --git a/gcc/target.def b/gcc/target.def
> > index ed2da154e30..268b56b6ebd 100644
> > --- a/gcc/target.def
> > +++ b/gcc/target.def
> > @@ -4452,7 +4452,8 @@ DEFHOOK
> >  (asan_shadow_offset,
> >   "Return the offset bitwise ored into shifted address to get
> > corresponding\n\
> >  Address Sanitizer shadow memory address.  NULL if Address Sanitizer is
> > not\n\
> > -supported by the target.",
> > +supported by the target.  May return 0 if Address Sanitizer is not
> > supported\n\
> > +by a subtarget.",
> >   unsigned HOST_WIDE_INT, (void),
> >   NULL)
> >
> > diff --git a/gcc/toplev.c b/gcc/toplev.c
> > index 20e231f4d2a..cf89598252c 100644
> > --- a/gcc/toplev.c
> > +++ b/gcc/toplev.c
> > @@ -1834,7 +1834,8 @@ process_options (void)
> >      }
> >
> >    if ((flag_sanitize & SANITIZE_USER_ADDRESS)
> > -      && targetm.asan_shadow_offset == NULL)
> > +      && ((targetm.asan_shadow_offset == NULL)
> > +         || (targetm.asan_shadow_offset () == 0)))
> >      {
> >        warning_at (UNKNOWN_LOCATION, 0,
> >                   "%<-fsanitize=address%> not supported for this target");
> > --
> > 2.17.1
> >
> >
Jim Wilson Nov. 11, 2020, 7:53 p.m. UTC | #3 
Original message here
https://gcc.gnu.org/pipermail/gcc-patches/2020-October/557406.html

This has non-RISC-V changes, so I need a global reviewer to look at it.

Jim

On Wed, Nov 4, 2020 at 12:10 PM Jim Wilson <jimw@sifive.com> wrote:

>
>
> On Wed, Oct 28, 2020 at 4:59 PM Jim Wilson <jimw@sifive.com> wrote:
>
>> We have only riscv64 asan support, there is no riscv32 support as yet.
>> So I
>> need to be able to conditionally enable asan support for the riscv
>> target.  I
>> implemented this by returning zero from the asan_shadow_offset function.
>> This
>> requires a change to toplev.c and docs in target.def.
>>
>> The asan support works on a 5.5 kernel, but does not work on a 4.15
>> kernel.
>> The problem is that the asan high memory region is a small wedge below
>> 0x4000000000.  The new kernel puts shared libraries at 0x3fffffffff and
>> going
>> down which works.  But the old kernel puts shared libraries at
>> 0x2000000000
>> and going up which does not work, as it isn't in any recognized memory
>> region.  This might be fixable with more asan work, but we don't really
>> need
>> support for old kernel versions.
>>
>> The asan port is curious in that it uses 1<<29 for the shadow offset, but
>> all
>> other 64-bit targets use a number larger than 1<<32.  But what we have is
>> working OK for now.
>>
>> I did a make check RUNTESTFLAGS="asan.exp" on Fedora rawhide image
>> running on
>> qemu and the results look reasonable.
>>
>>                 === gcc Summary ===
>>
>> # of expected passes            1905
>> # of unexpected failures        11
>> # of unsupported tests          224
>>
>>                 === g++ Summary ===
>>
>> # of expected passes            2002
>> # of unexpected failures        6
>> # of unresolved testcases       1
>> # of unsupported tests          175
>>
>> OK?
>>
>> Jim
>>
>> 2020-10-28  Jim Wilson  <jimw@sifive.com>
>>
>>         gcc/
>>         * config/riscv/riscv.c (riscv_asan_shadow_offset): New.
>>         (TARGET_ASAN_SHADOW_OFFSET): New.
>>         * doc/tm.texi: Regenerated.
>>         * target.def (asan_shadow_offset); Mention that it can return
>> zero.
>>         * toplev.c (process_options): Check for and handle zero return
>> from
>>         targetm.asan_shadow_offset call.
>>
>> Co-Authored-By: cooper.joshua <cooper.joshua@linux.alibaba.com>
>> ---
>>  gcc/config/riscv/riscv.c | 16 ++++++++++++++++
>>  gcc/doc/tm.texi          |  3 ++-
>>  gcc/target.def           |  3 ++-
>>  gcc/toplev.c             |  3 ++-
>>  4 files changed, 22 insertions(+), 3 deletions(-)
>>
>> diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c
>> index 989a9f15250..6909e200de1 100644
>> --- a/gcc/config/riscv/riscv.c
>> +++ b/gcc/config/riscv/riscv.c
>> @@ -5299,6 +5299,19 @@ riscv_gpr_save_operation_p (rtx op)
>>    return true;
>>  }
>>
>> +/* Implement TARGET_ASAN_SHADOW_OFFSET.  */
>> +
>> +static unsigned HOST_WIDE_INT
>> +riscv_asan_shadow_offset (void)
>> +{
>> +  /* We only have libsanitizer support for RV64 at present.
>> +
>> +     This number must match kRiscv*_ShadowOffset* in the file
>> +     libsanitizer/asan/asan_mapping.h which is currently 1<<29 for rv64,
>> +     even though 1<<36 makes more sense.  */
>> +  return TARGET_64BIT ? (HOST_WIDE_INT_1 << 29) : 0;
>> +}
>> +
>>  /* Initialize the GCC target structure.  */
>>  #undef TARGET_ASM_ALIGNED_HI_OP
>>  #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
>> @@ -5482,6 +5495,9 @@ riscv_gpr_save_operation_p (rtx op)
>>  #undef TARGET_NEW_ADDRESS_PROFITABLE_P
>>  #define TARGET_NEW_ADDRESS_PROFITABLE_P riscv_new_address_profitable_p
>>
>> +#undef TARGET_ASAN_SHADOW_OFFSET
>> +#define TARGET_ASAN_SHADOW_OFFSET riscv_asan_shadow_offset
>> +
>>  struct gcc_target targetm = TARGET_INITIALIZER;
>>
>>  #include "gt-riscv.h"
>> diff --git a/gcc/doc/tm.texi b/gcc/doc/tm.texi
>> index 24c37f655c8..39c596b647a 100644
>> --- a/gcc/doc/tm.texi
>> +++ b/gcc/doc/tm.texi
>> @@ -12078,7 +12078,8 @@ is zero, which disables this optimization.
>>  @deftypefn {Target Hook} {unsigned HOST_WIDE_INT}
>> TARGET_ASAN_SHADOW_OFFSET (void)
>>  Return the offset bitwise ored into shifted address to get corresponding
>>  Address Sanitizer shadow memory address.  NULL if Address Sanitizer is
>> not
>> -supported by the target.
>> +supported by the target.  May return 0 if Address Sanitizer is not
>> supported
>> +by a subtarget.
>>  @end deftypefn
>>
>>  @deftypefn {Target Hook} {unsigned HOST_WIDE_INT} TARGET_MEMMODEL_CHECK
>> (unsigned HOST_WIDE_INT @var{val})
>> diff --git a/gcc/target.def b/gcc/target.def
>> index ed2da154e30..268b56b6ebd 100644
>> --- a/gcc/target.def
>> +++ b/gcc/target.def
>> @@ -4452,7 +4452,8 @@ DEFHOOK
>>  (asan_shadow_offset,
>>   "Return the offset bitwise ored into shifted address to get
>> corresponding\n\
>>  Address Sanitizer shadow memory address.  NULL if Address Sanitizer is
>> not\n\
>> -supported by the target.",
>> +supported by the target.  May return 0 if Address Sanitizer is not
>> supported\n\
>> +by a subtarget.",
>>   unsigned HOST_WIDE_INT, (void),
>>   NULL)
>>
>> diff --git a/gcc/toplev.c b/gcc/toplev.c
>> index 20e231f4d2a..cf89598252c 100644
>> --- a/gcc/toplev.c
>> +++ b/gcc/toplev.c
>> @@ -1834,7 +1834,8 @@ process_options (void)
>>      }
>>
>>    if ((flag_sanitize & SANITIZE_USER_ADDRESS)
>> -      && targetm.asan_shadow_offset == NULL)
>> +      && ((targetm.asan_shadow_offset == NULL)
>> +         || (targetm.asan_shadow_offset () == 0)))
>>      {
>>        warning_at (UNKNOWN_LOCATION, 0,
>>                   "%<-fsanitize=address%> not supported for this target");
>> --
>> 2.17.1
>>
>>
Jeff Law Nov. 13, 2020, 7:12 p.m. UTC | #4 
On 10/28/20 5:58 PM, Jim Wilson wrote:
> We have only riscv64 asan support, there is no riscv32 support as yet.  So I
> need to be able to conditionally enable asan support for the riscv target.  I
> implemented this by returning zero from the asan_shadow_offset function.  This
> requires a change to toplev.c and docs in target.def.
>
> The asan support works on a 5.5 kernel, but does not work on a 4.15 kernel.
> The problem is that the asan high memory region is a small wedge below
> 0x4000000000.  The new kernel puts shared libraries at 0x3fffffffff and going
> down which works.  But the old kernel puts shared libraries at 0x2000000000
> and going up which does not work, as it isn't in any recognized memory
> region.  This might be fixable with more asan work, but we don't really need
> support for old kernel versions.
>
> The asan port is curious in that it uses 1<<29 for the shadow offset, but all
> other 64-bit targets use a number larger than 1<<32.  But what we have is
> working OK for now.
>
> I did a make check RUNTESTFLAGS="asan.exp" on Fedora rawhide image running on
> qemu and the results look reasonable.
>
> 		=== gcc Summary ===
>
> # of expected passes		1905
> # of unexpected failures	11
> # of unsupported tests		224
>
> 		=== g++ Summary ===
>
> # of expected passes		2002
> # of unexpected failures	6
> # of unresolved testcases	1
> # of unsupported tests		175
>
> OK?
>
> Jim
>
> 2020-10-28  Jim Wilson  <jimw@sifive.com>
>
> 	gcc/
> 	* config/riscv/riscv.c (riscv_asan_shadow_offset): New.
> 	(TARGET_ASAN_SHADOW_OFFSET): New.
> 	* doc/tm.texi: Regenerated.
> 	* target.def (asan_shadow_offset); Mention that it can return zero.
> 	* toplev.c (process_options): Check for and handle zero return from
> 	targetm.asan_shadow_offset call.

I noticed you hadn't committed this change.  Just to be explicit, this
is OK for the trunk.


Thanks,

jeff
Jim Wilson Nov. 14, 2020, 3:11 a.m. UTC | #5 
On Fri, Nov 13, 2020 at 11:12 AM Jeff Law <law@redhat.com> wrote:

>
> On 10/28/20 5:58 PM, Jim Wilson wrote:
> > We have only riscv64 asan support, there is no riscv32 support as yet.
> So I
> > need to be able to conditionally enable asan support for the riscv
> target.  I
> > implemented this by returning zero from the asan_shadow_offset
> function.  This
> > requires a change to toplev.c and docs in target.def.
> >
>


> I noticed you hadn't committed this change.  Just to be explicit, this
> is OK for the trunk.
>

Thanks committed.  I can self approve the RISC-V parts but not the asan
changes so I wanted a review for that.

Jim
diff mbox series

Patch

diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c
index 989a9f15250..6909e200de1 100644
--- a/gcc/config/riscv/riscv.c
+++ b/gcc/config/riscv/riscv.c
@@ -5299,6 +5299,19 @@  riscv_gpr_save_operation_p (rtx op)
   return true;
 }
 
+/* Implement TARGET_ASAN_SHADOW_OFFSET.  */
+
+static unsigned HOST_WIDE_INT
+riscv_asan_shadow_offset (void)
+{
+  /* We only have libsanitizer support for RV64 at present.
+
+     This number must match kRiscv*_ShadowOffset* in the file
+     libsanitizer/asan/asan_mapping.h which is currently 1<<29 for rv64,
+     even though 1<<36 makes more sense.  */
+  return TARGET_64BIT ? (HOST_WIDE_INT_1 << 29) : 0;
+}
+
 /* Initialize the GCC target structure.  */
 #undef TARGET_ASM_ALIGNED_HI_OP
 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
@@ -5482,6 +5495,9 @@  riscv_gpr_save_operation_p (rtx op)
 #undef TARGET_NEW_ADDRESS_PROFITABLE_P
 #define TARGET_NEW_ADDRESS_PROFITABLE_P riscv_new_address_profitable_p
 
+#undef TARGET_ASAN_SHADOW_OFFSET
+#define TARGET_ASAN_SHADOW_OFFSET riscv_asan_shadow_offset
+
 struct gcc_target targetm = TARGET_INITIALIZER;
 
 #include "gt-riscv.h"
diff --git a/gcc/doc/tm.texi b/gcc/doc/tm.texi
index 24c37f655c8..39c596b647a 100644
--- a/gcc/doc/tm.texi
+++ b/gcc/doc/tm.texi
@@ -12078,7 +12078,8 @@  is zero, which disables this optimization.
 @deftypefn {Target Hook} {unsigned HOST_WIDE_INT} TARGET_ASAN_SHADOW_OFFSET (void)
 Return the offset bitwise ored into shifted address to get corresponding
 Address Sanitizer shadow memory address.  NULL if Address Sanitizer is not
-supported by the target.
+supported by the target.  May return 0 if Address Sanitizer is not supported
+by a subtarget.
 @end deftypefn
 
 @deftypefn {Target Hook} {unsigned HOST_WIDE_INT} TARGET_MEMMODEL_CHECK (unsigned HOST_WIDE_INT @var{val})
diff --git a/gcc/target.def b/gcc/target.def
index ed2da154e30..268b56b6ebd 100644
--- a/gcc/target.def
+++ b/gcc/target.def
@@ -4452,7 +4452,8 @@  DEFHOOK
 (asan_shadow_offset,
  "Return the offset bitwise ored into shifted address to get corresponding\n\
 Address Sanitizer shadow memory address.  NULL if Address Sanitizer is not\n\
-supported by the target.",
+supported by the target.  May return 0 if Address Sanitizer is not supported\n\
+by a subtarget.",
  unsigned HOST_WIDE_INT, (void),
  NULL)
 
diff --git a/gcc/toplev.c b/gcc/toplev.c
index 20e231f4d2a..cf89598252c 100644
--- a/gcc/toplev.c
+++ b/gcc/toplev.c
@@ -1834,7 +1834,8 @@  process_options (void)
     }
 
   if ((flag_sanitize & SANITIZE_USER_ADDRESS)
-      && targetm.asan_shadow_offset == NULL)
+      && ((targetm.asan_shadow_offset == NULL)
+	  || (targetm.asan_shadow_offset () == 0)))
     {
       warning_at (UNKNOWN_LOCATION, 0,
 		  "%<-fsanitize=address%> not supported for this target");