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[114.34.229.221]) by smtp.gmail.com with ESMTPSA id t10sm3245939pgp.15.2020.09.09.20.44.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Sep 2020 20:44:15 -0700 (PDT) From: Kito Cheng To: gcc-patches@gcc.gnu.org, kito.cheng@gmail.com, rguenther@suse.de Subject: [PATCH] PR target/96759 - Handle global variable assignment from misaligned structure/PARALLEL return values. Date: Thu, 10 Sep 2020 11:44:05 +0800 Message-Id: <20200910034405.39647-1-kito.cheng@sifive.com> X-Mailer: git-send-email 2.28.0 MIME-Version: 1.0 X-Spam-Status: No, score=-14.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kito Cheng Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" In g:70cdb21e579191fe9f0f1d45e328908e59c0179e, DECL/global variable has handled misaligned stores, but it didn't handle PARALLEL values, and I refer the other part of this function, I found the PARALLEL need handled by emit_group_* functions, so I add a check, and using emit_group_store if storing a PARALLEL value, also checked this change didn't break the testcase(gcc.target/arm/unaligned-argument-3.c) added by the orginal changes. For riscv64 target, struct S {int a; double b;} will pack into a parallel value to return and it has TImode when misaligned access is supported, however TImode required 16-byte align, but it only 8-byte align, so it go to the misaligned stores handling, then it will try to generate move instruction from a PARALLEL value. Tested on following target without introduced new reguression: - riscv32/riscv64 elf - x86_64-linux - arm-eabi gcc/ChangeLog: PR target/96759 * expr.c (expand_assignment): Handle misaligned stores with PARALLEL value. gcc/testsuite/ChangeLog: PR target/96759 * g++.target/riscv/pr96759.C: New. * gcc.target/riscv/pr96759.c: New. --- gcc/expr.c | 9 ++++++++- gcc/testsuite/g++.target/riscv/pr96759.C | 8 ++++++++ gcc/testsuite/gcc.target/riscv/pr96759.c | 13 +++++++++++++ 3 files changed, 29 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/g++.target/riscv/pr96759.C create mode 100644 gcc/testsuite/gcc.target/riscv/pr96759.c diff --git a/gcc/expr.c b/gcc/expr.c index 1a15f24b3979..cc2bc52c457f 100644 --- a/gcc/expr.c +++ b/gcc/expr.c @@ -5173,7 +5173,14 @@ expand_assignment (tree to, tree from, bool nontemporal) if (TREE_CODE (to) == MEM_REF && REF_REVERSE_STORAGE_ORDER (to)) reg = flip_storage_order (mode, reg); - if (icode != CODE_FOR_nothing) + if (GET_CODE (reg) == PARALLEL) + { + push_temp_slots (); + emit_group_store (mem, reg, TREE_TYPE (from), + int_size_in_bytes (TREE_TYPE (from))); + pop_temp_slots (); + } + else if (icode != CODE_FOR_nothing) { class expand_operand ops[2]; diff --git a/gcc/testsuite/g++.target/riscv/pr96759.C b/gcc/testsuite/g++.target/riscv/pr96759.C new file mode 100644 index 000000000000..673999a4baf7 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/pr96759.C @@ -0,0 +1,8 @@ +/* { dg-options "-mno-strict-align -std=gnu++17" } */ +/* { dg-do compile } */ +struct S { + int a; + double b; +}; +S GetNumbers(); +auto [globalC, globalD] = GetNumbers(); diff --git a/gcc/testsuite/gcc.target/riscv/pr96759.c b/gcc/testsuite/gcc.target/riscv/pr96759.c new file mode 100644 index 000000000000..621c39196fca --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr96759.c @@ -0,0 +1,13 @@ +/* { dg-options "-mno-strict-align" } */ +/* { dg-do compile } */ + +struct S { + int a; + double b; +}; +struct S GetNumbers(); +struct S g; + +void foo(){ + g = GetNumbers(); +}