From patchwork Thu Aug 27 17:11:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Coplan X-Patchwork-Id: 1352723 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=sourceware.org; envelope-from=gcc-patches-bounces@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=armh.onmicrosoft.com header.i=@armh.onmicrosoft.com header.a=rsa-sha256 header.s=selector2-armh-onmicrosoft-com header.b=xEKrpkMI; dkim=pass (1024-bit key) header.d=armh.onmicrosoft.com header.i=@armh.onmicrosoft.com header.a=rsa-sha256 header.s=selector2-armh-onmicrosoft-com header.b=xEKrpkMI; dkim-atps=neutral Received: from sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Bcq6d6B0tz9sSP for ; Fri, 28 Aug 2020 03:12:40 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id A372A38708D5; Thu, 27 Aug 2020 17:12:37 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from EUR02-AM5-obe.outbound.protection.outlook.com (mail-eopbgr00062.outbound.protection.outlook.com [40.107.0.62]) by sourceware.org (Postfix) with ESMTPS id 158A63836C5C for ; Thu, 27 Aug 2020 17:12:32 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 158A63836C5C Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=Alex.Coplan@arm.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=c0uWiqNiEPiEQxhBzQ6zA0CR1J2ASoMsGGtibLZt7jo=; b=xEKrpkMIeoz96X38+5Vwnw4e7+a8OTxDc61cTBzZTG8FhSzu2RSnYR8mDYAcFUIlRS5fbTAU0Du64xqHu5Yv3FxSLKeD0aIc3Hi9D1esaMGYKWKXviqXIscWRgFEBz9vVnotYd3BUZRFhSyBfnBUJtmQHqo8MRm0r8NzaLoxcEA= Received: from AM6P194CA0074.EURP194.PROD.OUTLOOK.COM (2603:10a6:209:8f::15) by DB7PR08MB3915.eurprd08.prod.outlook.com (2603:10a6:10:34::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3305.24; Thu, 27 Aug 2020 17:12:29 +0000 Received: from VE1EUR03FT053.eop-EUR03.prod.protection.outlook.com (2603:10a6:209:8f:cafe::12) by AM6P194CA0074.outlook.office365.com (2603:10a6:209:8f::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3326.19 via Frontend Transport; Thu, 27 Aug 2020 17:12:29 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 63.35.35.123) smtp.mailfrom=arm.com; gcc.gnu.org; dkim=pass (signature was verified) header.d=armh.onmicrosoft.com;gcc.gnu.org; dmarc=bestguesspass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 63.35.35.123 as permitted sender) receiver=protection.outlook.com; client-ip=63.35.35.123; helo=64aa7808-outbound-1.mta.getcheckrecipient.com; Received: from 64aa7808-outbound-1.mta.getcheckrecipient.com (63.35.35.123) by VE1EUR03FT053.mail.protection.outlook.com (10.152.19.198) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3326.19 via Frontend Transport; Thu, 27 Aug 2020 17:12:28 +0000 Received: ("Tessian outbound 195a290eb161:v64"); Thu, 27 Aug 2020 17:12:28 +0000 X-CheckRecipientChecked: true X-CR-MTA-CID: d6d03339e508811f X-CR-MTA-TID: 64aa7808 Received: from ab1212750ff6.2 by 64aa7808-outbound-1.mta.getcheckrecipient.com id F3FD1618-3121-4A75-AC24-73F099F7D3B5.1; Thu, 27 Aug 2020 17:11:51 +0000 Received: from EUR02-VE1-obe.outbound.protection.outlook.com by 64aa7808-outbound-1.mta.getcheckrecipient.com with ESMTPS id ab1212750ff6.2 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384); Thu, 27 Aug 2020 17:11:51 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Ovw9t80AOcV4jivRe7crm+d+mOfkiyhLlv7/RszDjSTFvJ2NBHRBCwIzJSXNJfvEhxvN0cLcl5xuH5Oy8FTCzc4zeE+VgHTfd0/pFyUpIhYIMcPwY3fFzWXp8/8/Qt3encLYLt8BpC9czXh1/xstmkfvvEQVExfBqoW1fsEysSOm3Ep53q6/f084rlEWuwjAN5Wia/GTnlW5ot8V0qNsm2KRmzgmMMMtYiUg+5mzgavWPhatX3Sl9VZEXmI4VUzU28gx9c8fw2N+eoPXHSe2kvPn9kUTrIxONCw47B9qz5hroRYc9OV4CL4EdRN2qe1byeNOzbJC++OOTA+k5WfUKQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=c0uWiqNiEPiEQxhBzQ6zA0CR1J2ASoMsGGtibLZt7jo=; b=Po7dtgLWwm2R0GoscFS07R2FOXo/76EnLIiLNVjBMAXtBJThuj6NVmB9W5N4BFsk0VNO74qhS7qjKriy1iXG4+34qdjAkQdIQgkANVjwhlpuw6oLJ+V/y1vA2BktSfIXza77Mb1lVuSDYed2DS91AyFXBiQbkfIh+cXJaGuK2pHyCFE2mfFpQp1BWt5OWp3xpAhf937j3DyucgIps2dtBK2qWvHqGuiJDG9COM1ZK4JnAf2NAV/5paY0AoeIhuvZBrDofebQsHzz7mDBBKW1AgpZsGJg7t+PeNP0GqvyM/O3crl/VLbmMXQ+7FSxMzy/abqvXtVRHMHpV8QQk5C07g== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=arm.com; dmarc=pass action=none header.from=arm.com; dkim=pass header.d=arm.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=c0uWiqNiEPiEQxhBzQ6zA0CR1J2ASoMsGGtibLZt7jo=; b=xEKrpkMIeoz96X38+5Vwnw4e7+a8OTxDc61cTBzZTG8FhSzu2RSnYR8mDYAcFUIlRS5fbTAU0Du64xqHu5Yv3FxSLKeD0aIc3Hi9D1esaMGYKWKXviqXIscWRgFEBz9vVnotYd3BUZRFhSyBfnBUJtmQHqo8MRm0r8NzaLoxcEA= Authentication-Results-Original: gcc.gnu.org; dkim=none (message not signed) header.d=none;gcc.gnu.org; dmarc=none action=none header.from=arm.com; Received: from VI1PR08MB4029.eurprd08.prod.outlook.com (2603:10a6:803:ec::14) by VI1PR08MB3919.eurprd08.prod.outlook.com (2603:10a6:803:c4::31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3326.19; Thu, 27 Aug 2020 17:11:49 +0000 Received: from VI1PR08MB4029.eurprd08.prod.outlook.com ([fe80::c194:c7c6:f09e:6f3d]) by VI1PR08MB4029.eurprd08.prod.outlook.com ([fe80::c194:c7c6:f09e:6f3d%7]) with mapi id 15.20.3326.021; Thu, 27 Aug 2020 17:11:49 +0000 Date: Thu, 27 Aug 2020 18:11:47 +0100 From: Alex Coplan To: gcc-patches@gcc.gnu.org Subject: [PATCH] aarch64: Remove redundant mult patterns Message-ID: <20200827171146.7vp5fro2rvlecllc@arm.com> Content-Disposition: inline User-Agent: NeoMutt/20171215 X-ClientProxiedBy: LO2P265CA0219.GBRP265.PROD.OUTLOOK.COM (2603:10a6:600:b::15) To VI1PR08MB4029.eurprd08.prod.outlook.com (2603:10a6:803:ec::14) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from arm.com (217.140.106.50) by LO2P265CA0219.GBRP265.PROD.OUTLOOK.COM (2603:10a6:600:b::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3326.19 via Frontend Transport; Thu, 27 Aug 2020 17:11:49 +0000 X-Originating-IP: [217.140.106.50] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: aaf716be-84d9-469b-ebf4-08d84aac60a4 X-MS-TrafficTypeDiagnostic: VI1PR08MB3919:|DB7PR08MB3915: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: x-checkrecipientrouted: true NoDisclaimer: true X-MS-Oob-TLC-OOBClassifiers: OLM:8882;OLM:8882; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: BL2CTWG80RhlvP7GDxC17cd5/zLrWZ87n+6tgD4sS58soJofvhhoIwV5UV7KBXAO8EqGEkoW1bE3moORPysVMHhyFurA1Pn5JOGKjuQNhrjOtqMdUzJcej1l/iDDB/8nQwrOHq0dgm0gtKtzteJe7f5BUerTjteq1GWcY8r7bz+Aj1XxNfTLV10151ViGZ4qv4bCDud20ALYEx2LNxCBAk56/wow5iyE86KcGWy1Ax4JMSYAQFcE6MQIv4nma12J3g4YzlE5IlR2h0+GNsQUxeeDfSzpbM05bfgP8jivWN1nghCAeK7ZJMX200UXy/4ZgYD3QN34M4kb756dK5KTfTDlsVH+qWqg3l+R9hVFDJnjyJqd+sbeMEQmfiyYiCHCBhkURUttj460IfxUOsxJc2dehIwLb2xNCV3IrR5nsZfq80EKbmqr3cCB9LAH0wdZ1HzzMuNGTdKFeswkgSO+cA== X-Forefront-Antispam-Report-Untrusted: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:VI1PR08MB4029.eurprd08.prod.outlook.com; PTR:; CAT:NONE; SFS:(4636009)(346002)(376002)(136003)(396003)(39860400002)(366004)(52116002)(16526019)(186003)(33964004)(44144004)(1076003)(4326008)(2616005)(44832011)(7696005)(2906002)(956004)(26005)(36756003)(66476007)(66946007)(235185007)(8936002)(83380400001)(8676002)(86362001)(966005)(6916009)(8886007)(316002)(5660300002)(21480400003)(66556008)(54906003)(66616009)(55016002)(478600001)(2700100001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData: qIOuFnsIBiJva2HAgGfqqEpQyQCjMMHFo0gko25S1RcES/t+P3tYLz4Bg/hv4ZSp3L9R72VqxVZWnqFWLGgP/MYohoWQrCRInx2QT4ojh+FywE1Oe4a1UAvyRWqQLJyu1yHCOFSVuT5eBwWLwLlKiwXnT708kaB/8x5YTegnRBavACDBTbaIvPnO/NpuvcVyJCluJxquEztintff+M9nVCdnkoMT38jPdt5Knt6vqkWB4Fhc/ktk0+P40D1GFbSj0VWCqYCAJoljbsgeJMzGhHcZpXR77yrBL2mjWdAxclOM6kgrCua0JRKOZsEKvXNmjASeZzNc0++pi3WWTsrVOJxrP4FrzAotjA9W7H2T+r0Isdt7oQZpimh9PxiQJoo8+URqXmgnHSbwg68dEVChGfCgLDsFV/oyklE6XqtUFe9R5OnYB2aOY+xh0j41+X9UD/u6bwFCqaRNyDbDHIO56ZD9Jwr8CjxId2i1N/bgS06/HoCsAaLdWufewTgc9YWXt6pQJIoyCFG22tJwCh0oQq1UVeSAhbU0JZThRzsR7gLcGBN8TULToMhj5cJK0F9NoHoa7aHP4kE6cezbxw0pHODGtZQ55QhNLKCR8DgTqyktBYXVHSQQyWmxyD5/P4q365GtciUf2uJVHL+wr4lYYw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR08MB3919 Original-Authentication-Results: gcc.gnu.org; dkim=none (message not signed) header.d=none;gcc.gnu.org; dmarc=none action=none header.from=arm.com; X-EOPAttributedMessage: 0 X-MS-Exchange-Transport-CrossTenantHeadersStripped: VE1EUR03FT053.eop-EUR03.prod.protection.outlook.com X-MS-Office365-Filtering-Correlation-Id-Prvs: 2d6dc357-bd2a-4caa-e64b-08d84aac4912 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: CQ+9ElE5tNDqVFb9fRhy1+bqK1ruZR1TIxy20S0CYgJWanAI+OeydQbYGrHxIFSw2t6OURMgW1YxXsKTygBY97xhobXOCv2OXri+jGkzLmjS8wecQ2mL1Q5q5W/aXb1H1J6mITMxZmZwWx9FIHjSZu1HOAgum1Ra1RTrlpZdY1vKLAeokrmE1Mnp8ulI+dH5urTX1+cmX2c2HEVVJsbK4iYh4thyl//VFLSwD0MYswui1p4xd4whsBG7gXKJKB+5eglINbIXBor1U1xQC0X1kduayUARNxNc9jm9SIEVNJb2K7C2JHBPxQVDs6sUB/8N7Lgdl4Cuvpur8MJRNSepb7EFBFb6V31mmvamtpLTW3NdLjZO9tksuysoVHGnQZPkd2ywxpPBjXzM1Yd8jR6lstVUEQt5vVHcEA/oioN+E9Of6ojQybrdh4sNfKJ8/0z8Q4/491wMwsk3EOHrWzGPsB/fIy/mtGUUWgw2cZpRpD8ANU1Qq4PYBbyFaB4RWqO2 X-Forefront-Antispam-Report: CIP:63.35.35.123; CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFS:(4636009)(396003)(376002)(346002)(136003)(39860400002)(46966005)(186003)(6916009)(7696005)(478600001)(16526019)(8886007)(4326008)(21480400003)(966005)(33964004)(44144004)(55016002)(86362001)(26005)(356005)(82740400003)(5660300002)(235185007)(83380400001)(8676002)(2616005)(316002)(47076004)(81166007)(54906003)(1076003)(956004)(8936002)(36756003)(70586007)(44832011)(70206006)(2906002)(36906005)(336012)(66616009)(82310400002)(2700100001); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Aug 2020 17:12:28.7684 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: aaf716be-84d9-469b-ebf4-08d84aac60a4 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: VE1EUR03FT053.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB7PR08MB3915 X-Spam-Status: No, score=-15.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, KAM_SHORT, MSGID_FROM_MTA_HEADER, RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Earnshaw , Marcus Shawcroft Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" Hello, Following on from the earlier patch to fix up the syntax for add/sub/adds/subs and friends with a sign/zero-extended operand [0], this patch removes the "mult" variants of these patterns which are all redundant. This patch removes the following patterns from the AArch64 backend: *adds_mul_imm_ *subs_mul_imm_ *adds__multp2 *subs__multp2 *add_mul_imm_ *add__mult_ *add__mult_si_uxtw *add__multp2 *add_si_multp2_uxtw *add_uxt_multp2 *add_uxtsi_multp2_uxtw *sub_mul_imm_ *sub_mul_imm_si_uxtw *sub__multp2 *sub_si_multp2_uxtw *sub_uxt_multp2 *sub_uxtsi_multp2_uxtw *neg_mul_imm_2 *neg_mul_imm_si2_uxtw Together with the following predicates which were used only by these patterns: - aarch64_pwr_imm3 - aarch64_pwr_2_si - aarch64_pwr_2_di These patterns are all redundant since multiplications by powers of two should be represented as shfits outside a (mem). Testing: * Bootstrapped and regtested on aarch64-none-linux-gnu (on top of [0]), no regressions. OK for master (when applied after [0])? Thanks, Alex [0] : https://gcc.gnu.org/pipermail/gcc-patches/2020-August/552137.html --- gcc/ChangeLog: * config/aarch64/aarch64.md (*adds_mul_imm_): Delete. (*subs_mul_imm_): Delete. (*adds__multp2): Delete. (*subs__multp2): Delete. (*add_mul_imm_): Delete. (*add__mult_): Delete. (*add__mult_si_uxtw): Delete. (*add__multp2): Delete. (*add_si_multp2_uxtw): Delete. (*add_uxt_multp2): Delete. (*add_uxtsi_multp2_uxtw): Delete. (*sub_mul_imm_): Delete. (*sub_mul_imm_si_uxtw): Delete. (*sub__multp2): Delete. (*sub_si_multp2_uxtw): Delete. (*sub_uxt_multp2): Delete. (*sub_uxtsi_multp2_uxtw): Delete. (*neg_mul_imm_2): Delete. (*neg_mul_imm_si2_uxtw): Delete. * config/aarch64/predicates.md (aarch64_pwr_imm3): Delete. (aarch64_pwr_2_si): Delete. (aarch64_pwr_2_di): Delete. diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 9b20dd0b1a0..59516db4b77 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -2341,38 +2341,6 @@ [(set_attr "type" "alus_shift_imm")] ) -(define_insn "*adds_mul_imm_" - [(set (reg:CC_NZ CC_REGNUM) - (compare:CC_NZ - (plus:GPI (mult:GPI - (match_operand:GPI 1 "register_operand" "r") - (match_operand:QI 2 "aarch64_pwr_2_" "n")) - (match_operand:GPI 3 "register_operand" "r")) - (const_int 0))) - (set (match_operand:GPI 0 "register_operand" "=r") - (plus:GPI (mult:GPI (match_dup 1) (match_dup 2)) - (match_dup 3)))] - "" - "adds\\t%0, %3, %1, lsl %p2" - [(set_attr "type" "alus_shift_imm")] -) - -(define_insn "*subs_mul_imm_" - [(set (reg:CC_NZ CC_REGNUM) - (compare:CC_NZ - (minus:GPI (match_operand:GPI 1 "register_operand" "r") - (mult:GPI - (match_operand:GPI 2 "register_operand" "r") - (match_operand:QI 3 "aarch64_pwr_2_" "n"))) - (const_int 0))) - (set (match_operand:GPI 0 "register_operand" "=r") - (minus:GPI (match_dup 1) - (mult:GPI (match_dup 2) (match_dup 3))))] - "" - "subs\\t%0, %1, %2, lsl %p3" - [(set_attr "type" "alus_shift_imm")] -) - (define_insn "*adds__" [(set (reg:CC_NZ CC_REGNUM) (compare:CC_NZ @@ -2437,46 +2405,6 @@ [(set_attr "type" "alus_ext")] ) -(define_insn "*adds__multp2" - [(set (reg:CC_NZ CC_REGNUM) - (compare:CC_NZ - (plus:GPI (ANY_EXTRACT:GPI - (mult:GPI (match_operand:GPI 1 "register_operand" "r") - (match_operand 2 "aarch64_pwr_imm3" "Up3")) - (match_operand 3 "const_int_operand" "n") - (const_int 0)) - (match_operand:GPI 4 "register_operand" "rk")) - (const_int 0))) - (set (match_operand:GPI 0 "register_operand" "=r") - (plus:GPI (ANY_EXTRACT:GPI (mult:GPI (match_dup 1) (match_dup 2)) - (match_dup 3) - (const_int 0)) - (match_dup 4)))] - "aarch64_is_extend_from_extract (mode, operands[2], operands[3])" - "adds\\t%0, %4, %1, xt%e3 %p2" - [(set_attr "type" "alus_ext")] -) - -(define_insn "*subs__multp2" - [(set (reg:CC_NZ CC_REGNUM) - (compare:CC_NZ - (minus:GPI (match_operand:GPI 4 "register_operand" "rk") - (ANY_EXTRACT:GPI - (mult:GPI (match_operand:GPI 1 "register_operand" "r") - (match_operand 2 "aarch64_pwr_imm3" "Up3")) - (match_operand 3 "const_int_operand" "n") - (const_int 0))) - (const_int 0))) - (set (match_operand:GPI 0 "register_operand" "=r") - (minus:GPI (match_dup 4) (ANY_EXTRACT:GPI - (mult:GPI (match_dup 1) (match_dup 2)) - (match_dup 3) - (const_int 0))))] - "aarch64_is_extend_from_extract (mode, operands[2], operands[3])" - "subs\\t%0, %4, %1, xt%e3 %p2" - [(set_attr "type" "alus_ext")] -) - (define_insn "*add3nr_compare0" [(set (reg:CC_NZ CC_REGNUM) (compare:CC_NZ @@ -2534,16 +2462,6 @@ [(set_attr "type" "alu_shift_imm")] ) -(define_insn "*add_mul_imm_" - [(set (match_operand:GPI 0 "register_operand" "=r") - (plus:GPI (mult:GPI (match_operand:GPI 1 "register_operand" "r") - (match_operand:QI 2 "aarch64_pwr_2_" "n")) - (match_operand:GPI 3 "register_operand" "r")))] - "" - "add\\t%0, %3, %1, lsl %p2" - [(set_attr "type" "alu_shift_imm")] -) - (define_insn "*add__" [(set (match_operand:GPI 0 "register_operand" "=rk") (plus:GPI (ANY_EXTEND:GPI (match_operand:ALLX 1 "register_operand" "r")) @@ -2588,57 +2506,6 @@ [(set_attr "type" "alu_ext")] ) -(define_insn "*add__mult_" - [(set (match_operand:GPI 0 "register_operand" "=rk") - (plus:GPI (mult:GPI (ANY_EXTEND:GPI - (match_operand:ALLX 1 "register_operand" "r")) - (match_operand 2 "aarch64_pwr_imm3" "Up3")) - (match_operand:GPI 3 "register_operand" "r")))] - "" - "add\\t%0, %3, %1, xt %p2" - [(set_attr "type" "alu_ext")] -) - -;; zero_extend version of above -(define_insn "*add__mult_si_uxtw" - [(set (match_operand:DI 0 "register_operand" "=rk") - (zero_extend:DI (plus:SI (mult:SI (ANY_EXTEND:SI - (match_operand:SHORT 1 "register_operand" "r")) - (match_operand 2 "aarch64_pwr_imm3" "Up3")) - (match_operand:SI 3 "register_operand" "r"))))] - "" - "add\\t%w0, %w3, %w1, xt %p2" - [(set_attr "type" "alu_ext")] -) - -(define_insn "*add__multp2" - [(set (match_operand:GPI 0 "register_operand" "=rk") - (plus:GPI (ANY_EXTRACT:GPI - (mult:GPI (match_operand:GPI 1 "register_operand" "r") - (match_operand 2 "aarch64_pwr_imm3" "Up3")) - (match_operand 3 "const_int_operand" "n") - (const_int 0)) - (match_operand:GPI 4 "register_operand" "r")))] - "aarch64_is_extend_from_extract (mode, operands[2], operands[3])" - "add\\t%0, %4, %1, xt%e3 %p2" - [(set_attr "type" "alu_ext")] -) - -;; zero_extend version of above -(define_insn "*add_si_multp2_uxtw" - [(set (match_operand:DI 0 "register_operand" "=rk") - (zero_extend:DI - (plus:SI (ANY_EXTRACT:SI - (mult:SI (match_operand:SI 1 "register_operand" "r") - (match_operand 2 "aarch64_pwr_imm3" "Up3")) - (match_operand 3 "const_int_operand" "n") - (const_int 0)) - (match_operand:SI 4 "register_operand" "r"))))] - "aarch64_is_extend_from_extract (SImode, operands[2], operands[3])" - "add\\t%w0, %w4, %w1, xt%e3 %p2" - [(set_attr "type" "alu_ext")] -) - (define_expand "add3_carryin" [(set (match_operand:GPI 0 "register_operand") (plus:GPI @@ -2840,38 +2707,6 @@ [(set_attr "type" "alu_ext")] ) -(define_insn "*add_uxt_multp2" - [(set (match_operand:GPI 0 "register_operand" "=rk") - (plus:GPI (and:GPI - (mult:GPI (match_operand:GPI 1 "register_operand" "r") - (match_operand 2 "aarch64_pwr_imm3" "Up3")) - (match_operand 3 "const_int_operand" "n")) - (match_operand:GPI 4 "register_operand" "r")))] - "aarch64_uxt_size (exact_log2 (INTVAL (operands[2])), INTVAL (operands[3])) != 0" - "* - operands[3] = GEN_INT (aarch64_uxt_size (exact_log2 (INTVAL (operands[2])), - INTVAL (operands[3]))); - return \"add\t%0, %4, %1, uxt%e3 %p2\";" - [(set_attr "type" "alu_ext")] -) - -;; zero_extend version of above -(define_insn "*add_uxtsi_multp2_uxtw" - [(set (match_operand:DI 0 "register_operand" "=rk") - (zero_extend:DI - (plus:SI (and:SI - (mult:SI (match_operand:SI 1 "register_operand" "r") - (match_operand 2 "aarch64_pwr_imm3" "Up3")) - (match_operand 3 "const_int_operand" "n")) - (match_operand:SI 4 "register_operand" "r"))))] - "aarch64_uxt_size (exact_log2 (INTVAL (operands[2])), INTVAL (operands[3])) != 0" - "* - operands[3] = GEN_INT (aarch64_uxt_size (exact_log2 (INTVAL (operands[2])), - INTVAL (operands[3]))); - return \"add\t%w0, %w4, %w1, uxt%e3 %p2\";" - [(set_attr "type" "alu_ext")] -) - (define_insn "subsi3" [(set (match_operand:SI 0 "register_operand" "=rk") (minus:SI (match_operand:SI 1 "register_operand" "rk") @@ -3275,30 +3110,6 @@ [(set_attr "type" "alu_shift_imm")] ) -(define_insn "*sub_mul_imm_" - [(set (match_operand:GPI 0 "register_operand" "=r") - (minus:GPI (match_operand:GPI 3 "register_operand" "r") - (mult:GPI - (match_operand:GPI 1 "register_operand" "r") - (match_operand:QI 2 "aarch64_pwr_2_" "n"))))] - "" - "sub\\t%0, %3, %1, lsl %p2" - [(set_attr "type" "alu_shift_imm")] -) - -;; zero_extend version of above -(define_insn "*sub_mul_imm_si_uxtw" - [(set (match_operand:DI 0 "register_operand" "=r") - (zero_extend:DI - (minus:SI (match_operand:SI 3 "register_operand" "r") - (mult:SI - (match_operand:SI 1 "register_operand" "r") - (match_operand:QI 2 "aarch64_pwr_2_si" "n")))))] - "" - "sub\\t%w0, %w3, %w1, lsl %p2" - [(set_attr "type" "alu_shift_imm")] -) - (define_insn "*sub__" [(set (match_operand:GPI 0 "register_operand" "=rk") (minus:GPI (match_operand:GPI 1 "register_operand" "rk") @@ -3345,34 +3156,6 @@ [(set_attr "type" "alu_ext")] ) -(define_insn "*sub__multp2" - [(set (match_operand:GPI 0 "register_operand" "=rk") - (minus:GPI (match_operand:GPI 4 "register_operand" "rk") - (ANY_EXTRACT:GPI - (mult:GPI (match_operand:GPI 1 "register_operand" "r") - (match_operand 2 "aarch64_pwr_imm3" "Up3")) - (match_operand 3 "const_int_operand" "n") - (const_int 0))))] - "aarch64_is_extend_from_extract (mode, operands[2], operands[3])" - "sub\\t%0, %4, %1, xt%e3 %p2" - [(set_attr "type" "alu_ext")] -) - -;; zero_extend version of above -(define_insn "*sub_si_multp2_uxtw" - [(set (match_operand:DI 0 "register_operand" "=rk") - (zero_extend:DI - (minus:SI (match_operand:SI 4 "register_operand" "rk") - (ANY_EXTRACT:SI - (mult:SI (match_operand:SI 1 "register_operand" "r") - (match_operand 2 "aarch64_pwr_imm3" "Up3")) - (match_operand 3 "const_int_operand" "n") - (const_int 0)))))] - "aarch64_is_extend_from_extract (SImode, operands[2], operands[3])" - "sub\\t%w0, %w4, %w1, xt%e3 %p2" - [(set_attr "type" "alu_ext")] -) - ;; The hardware description is op1 + ~op2 + C. ;; = op1 + (-op2 + 1) + (1 - !C) ;; = op1 - op2 - 1 + 1 - !C @@ -3628,38 +3411,6 @@ [(set_attr "type" "alu_ext")] ) -(define_insn "*sub_uxt_multp2" - [(set (match_operand:GPI 0 "register_operand" "=rk") - (minus:GPI (match_operand:GPI 4 "register_operand" "rk") - (and:GPI - (mult:GPI (match_operand:GPI 1 "register_operand" "r") - (match_operand 2 "aarch64_pwr_imm3" "Up3")) - (match_operand 3 "const_int_operand" "n"))))] - "aarch64_uxt_size (exact_log2 (INTVAL (operands[2])),INTVAL (operands[3])) != 0" - "* - operands[3] = GEN_INT (aarch64_uxt_size (exact_log2 (INTVAL (operands[2])), - INTVAL (operands[3]))); - return \"sub\t%0, %4, %1, uxt%e3 %p2\";" - [(set_attr "type" "alu_ext")] -) - -;; zero_extend version of above -(define_insn "*sub_uxtsi_multp2_uxtw" - [(set (match_operand:DI 0 "register_operand" "=rk") - (zero_extend:DI - (minus:SI (match_operand:SI 4 "register_operand" "rk") - (and:SI - (mult:SI (match_operand:SI 1 "register_operand" "r") - (match_operand 2 "aarch64_pwr_imm3" "Up3")) - (match_operand 3 "const_int_operand" "n")))))] - "aarch64_uxt_size (exact_log2 (INTVAL (operands[2])),INTVAL (operands[3])) != 0" - "* - operands[3] = GEN_INT (aarch64_uxt_size (exact_log2 (INTVAL (operands[2])), - INTVAL (operands[3]))); - return \"sub\t%w0, %w4, %w1, uxt%e3 %p2\";" - [(set_attr "type" "alu_ext")] -) - (define_expand "abs2" [(match_operand:GPI 0 "register_operand") (match_operand:GPI 1 "register_operand")] @@ -3772,28 +3523,6 @@ [(set_attr "type" "alu_shift_imm")] ) -(define_insn "*neg_mul_imm_2" - [(set (match_operand:GPI 0 "register_operand" "=r") - (neg:GPI (mult:GPI - (match_operand:GPI 1 "register_operand" "r") - (match_operand:QI 2 "aarch64_pwr_2_" "n"))))] - "" - "neg\\t%0, %1, lsl %p2" - [(set_attr "type" "alu_shift_imm")] -) - -;; zero_extend version of above -(define_insn "*neg_mul_imm_si2_uxtw" - [(set (match_operand:DI 0 "register_operand" "=r") - (zero_extend:DI - (neg:SI (mult:SI - (match_operand:SI 1 "register_operand" "r") - (match_operand:QI 2 "aarch64_pwr_2_si" "n")))))] - "" - "neg\\t%w0, %w1, lsl %p2" - [(set_attr "type" "alu_shift_imm")] -) - (define_insn "mul3" [(set (match_operand:GPI 0 "register_operand" "=r") (mult:GPI (match_operand:GPI 1 "register_operand" "r") diff --git a/gcc/config/aarch64/predicates.md b/gcc/config/aarch64/predicates.md index 1754b1eff9f..91b51483f33 100644 --- a/gcc/config/aarch64/predicates.md +++ b/gcc/config/aarch64/predicates.md @@ -235,21 +235,6 @@ (and (match_code "const_int") (match_test "IN_RANGE (UINTVAL (op), 0, 0xffffff)"))) -(define_predicate "aarch64_pwr_imm3" - (and (match_code "const_int") - (match_test "INTVAL (op) != 0 - && (unsigned) exact_log2 (INTVAL (op)) <= 4"))) - -(define_predicate "aarch64_pwr_2_si" - (and (match_code "const_int") - (match_test "INTVAL (op) != 0 - && (unsigned) exact_log2 (INTVAL (op)) < 32"))) - -(define_predicate "aarch64_pwr_2_di" - (and (match_code "const_int") - (match_test "INTVAL (op) != 0 - && (unsigned) exact_log2 (INTVAL (op)) < 64"))) - (define_predicate "aarch64_mem_pair_offset" (and (match_code "const_int") (match_test "aarch64_offset_7bit_signed_scaled_p (mode, INTVAL (op))")))