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[114.34.229.221]) by smtp.gmail.com with ESMTPSA id x3sm14021537pfn.154.2020.07.07.02.52.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jul 2020 02:52:19 -0700 (PDT) From: Kito Cheng To: gcc-patches@gcc.gnu.org, kito.cheng@gmail.com, jimw@sifive.com Subject: [PATCH] RISC-V: Implment __builtin_thread_pointer Date: Tue, 7 Jul 2020 17:52:14 +0800 Message-Id: <20200707095214.65476-1-kito.cheng@sifive.com> X-Mailer: git-send-email 2.27.0 MIME-Version: 1.0 X-Spam-Status: No, score=-14.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kito Cheng Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" RISC-V has a dedicate register for thread pointer which is specified in psABI doc, so we could support __builtin_thread_pointer in straightforward way. Note: clang/llvm was supported __builtin_thread_pointer for RISC-V port recently. - https://reviews.llvm.org/rGaabc24acf0d5f8677bd22fe9c108581e07c3e180 gcc/ChangeLog: * gcc/config/riscv/riscv.md (): New. (TP_REGNUM): Ditto. * doc/extend.texi (Target Builtins): Add RISC-V built-in section. Document __builtin_thread_pointer. gcc/testsuite/ChangeLog: * gcc.target/riscv/read-thread-pointer.c: New. --- gcc/config/riscv/riscv.md | 8 ++++++++ gcc/doc/extend.texi | 11 +++++++++++ gcc/testsuite/gcc.target/riscv/read-thread-pointer.c | 7 +++++++ 3 files changed, 26 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/read-thread-pointer.c diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 36012ad1f778..95a02ecaa34b 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -70,6 +70,7 @@ (define_constants [(RETURN_ADDR_REGNUM 1) (GP_REGNUM 3) + (TP_REGNUM 4) (T0_REGNUM 5) (T1_REGNUM 6) (S0_REGNUM 8) @@ -2515,6 +2516,13 @@ DONE; }) +;; Named pattern for expanding thread pointer reference. +(define_expand "get_thread_pointer" + [(set (match_operand:P 0 "register_operand" "=r") + (reg:P TP_REGNUM))] + "" +{}) + (include "sync.md") (include "peephole.md") (include "pic.md") diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index ecd3661d2571..556c98f46911 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -13859,6 +13859,7 @@ instructions, but allow the compiler to schedule those calls. * PowerPC Hardware Transactional Memory Built-in Functions:: * PowerPC Atomic Memory Operation Functions:: * PowerPC Matrix-Multiply Assist Built-in Functions:: +* RISC-V Built-in Functions:: * RX Built-in Functions:: * S/390 System z Built-in Functions:: * SH Built-in Functions:: @@ -21461,6 +21462,16 @@ vec_t __builtin_vsx_xvcvspbf16 (vec_t); vec_t __builtin_vsx_xvcvbf16sp (vec_t); @end smallexample +@node RISC-V Built-in Functions +@subsection RISC-V Built-in Functions + +These built-in functions are available for the RISC-V family of +processors. + +@deftypefn {Built-in Function} {void *} __builtin_thread_pointer (void) +Returns the value that is currently set in the @samp{tp} register. +@end deftypefn + @node RX Built-in Functions @subsection RX Built-in Functions GCC supports some of the RX instructions which cannot be expressed in diff --git a/gcc/testsuite/gcc.target/riscv/read-thread-pointer.c b/gcc/testsuite/gcc.target/riscv/read-thread-pointer.c new file mode 100644 index 000000000000..760f8eafb406 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/read-thread-pointer.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ + +void *get_tp() +{ + return __builtin_thread_pointer (); +} +/* { dg-final { scan-assembler "mv\[ \t\]*[at][0-9]+,tp" } } */