diff mbox series

[4/6] aarch64: Simplify @ccmp<cc_mode><mode> operands

Message ID 20200319064805.17739-5-richard.henderson@linaro.org
State New
Headers show
Series aarch64: Implement TImode comparisons | expand

Commit Message

Jeff Law via Gcc-patches March 19, 2020, 6:48 a.m. UTC
The first two arguments were "reversed", in that operand 0 was not
the output, but the input cc_reg.  Remove operand 0 entirely, since
we can get the input cc_reg from within the operand 3 comparison
expression.  This moves the output operand to index 0.

	* config/aarch64/aarch64.md (@ccmpcc<GPI>): New expander; remove
	operand 0; change operand 3 from match_operator to match_operand.
	(*ccmpcc<GPI>): Rename from @ccmp; swap numbers of operand 0 & 1.
	(@ccmp<CCFP_CCFPE><GPF>, *ccmp<CCFP_CCFPE><GPF>): Likewise.
	(@ccmpcc<GPI>_rev, *ccmpcc<GPI>_rev): Likewise.
	(@ccmp<CCFP_CCFPE><GPF>_rev, *ccmp<CCFP_CCFPE><GPF>_rev): Likewise.
	* config/aarch64/aarch64.c (aarch64_gen_compare_reg): Update to match.
	(aarch64_gen_ccmp_next): Likewise.
---
 gcc/config/aarch64/aarch64.c  | 21 +++++-----
 gcc/config/aarch64/aarch64.md | 76 +++++++++++++++++++++++++++++------
 2 files changed, 74 insertions(+), 23 deletions(-)
diff mbox series

Patch

diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 619357fa210..16ff40fc267 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -2349,7 +2349,7 @@  aarch64_gen_compare_reg (RTX_CODE code, rtx x, rtx y)
 
       rtx x_hi = operand_subword (x, 1, 0, TImode);
       rtx y_hi = operand_subword (y, 1, 0, TImode);
-      emit_insn (gen_ccmpccdi (cc_reg, cc_reg, x_hi, y_hi,
+      emit_insn (gen_ccmpccdi (cc_reg, x_hi, y_hi,
 			       gen_rtx_EQ (cc_mode, cc_reg, const0_rtx),
 			       GEN_INT (AARCH64_EQ)));
     }
@@ -20445,7 +20445,7 @@  aarch64_gen_ccmp_next (rtx_insn **prep_seq, rtx_insn **gen_seq, rtx prev,
   machine_mode op_mode, cmp_mode, cc_mode = CCmode;
   int unsignedp = TYPE_UNSIGNED (TREE_TYPE (treeop0));
   insn_code icode;
-  struct expand_operand ops[6];
+  struct expand_operand ops[5];
   int aarch64_cond;
 
   push_to_sequence (*prep_seq);
@@ -20484,8 +20484,8 @@  aarch64_gen_ccmp_next (rtx_insn **prep_seq, rtx_insn **gen_seq, rtx prev,
 
   icode = code_for_ccmp (cc_mode, cmp_mode);
 
-  op0 = prepare_operand (icode, op0, 2, op_mode, cmp_mode, unsignedp);
-  op1 = prepare_operand (icode, op1, 3, op_mode, cmp_mode, unsignedp);
+  op0 = prepare_operand (icode, op0, 1, op_mode, cmp_mode, unsignedp);
+  op1 = prepare_operand (icode, op1, 2, op_mode, cmp_mode, unsignedp);
   if (!op0 || !op1)
     {
       end_sequence ();
@@ -20517,15 +20517,14 @@  aarch64_gen_ccmp_next (rtx_insn **prep_seq, rtx_insn **gen_seq, rtx prev,
       aarch64_cond = AARCH64_INVERSE_CONDITION_CODE (aarch64_cond);
     }
 
-  create_fixed_operand (&ops[0], XEXP (prev, 0));
-  create_fixed_operand (&ops[1], target);
-  create_fixed_operand (&ops[2], op0);
-  create_fixed_operand (&ops[3], op1);
-  create_fixed_operand (&ops[4], prev);
-  create_fixed_operand (&ops[5], GEN_INT (aarch64_cond));
+  create_fixed_operand (&ops[0], target);
+  create_fixed_operand (&ops[1], op0);
+  create_fixed_operand (&ops[2], op1);
+  create_fixed_operand (&ops[3], prev);
+  create_fixed_operand (&ops[4], GEN_INT (aarch64_cond));
 
   push_to_sequence (*gen_seq);
-  if (!maybe_expand_insn (icode, 6, ops))
+  if (!maybe_expand_insn (icode, 5, ops))
     {
       end_sequence ();
       return NULL_RTX;
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 0fe41117640..12213176103 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -495,11 +495,24 @@ 
   ""
   "")
 
-(define_insn "@ccmp<CC_ONLY:mode><GPI:mode>"
-  [(set (match_operand:CC_ONLY 1 "cc_register" "")
+(define_expand "@ccmp<CC_ONLY:mode><GPI:mode>"
+  [(set (match_operand:CC_ONLY 0 "cc_register")
+	(if_then_else:CC_ONLY
+	  (match_operand 3 "aarch64_comparison_operator")
+	  (compare:CC_ONLY
+	    (match_operand:GPI 1 "aarch64_reg_or_zero")
+	    (match_operand:GPI 2 "aarch64_ccmp_operand"))
+	  (unspec:CC_ONLY
+	    [(match_operand 4 "immediate_operand")]
+	    UNSPEC_NZCV)))]
+  ""
+)
+
+(define_insn "*ccmp<CC_ONLY:mode><GPI:mode>"
+  [(set (match_operand:CC_ONLY 0 "cc_register" "")
 	(if_then_else:CC_ONLY
 	  (match_operator 4 "aarch64_comparison_operator"
-	   [(match_operand 0 "cc_register" "")
+	   [(match_operand 1 "cc_register" "")
 	    (const_int 0)])
 	  (compare:CC_ONLY
 	    (match_operand:GPI 2 "aarch64_reg_or_zero" "rZ,rZ,rZ")
@@ -515,11 +528,24 @@ 
   [(set_attr "type" "alus_sreg,alus_imm,alus_imm")]
 )
 
-(define_insn "@ccmp<CCFP_CCFPE:mode><GPF:mode>"
-  [(set (match_operand:CCFP_CCFPE 1 "cc_register" "")
+(define_expand "@ccmp<CCFP_CCFPE:mode><GPF:mode>"
+  [(set (match_operand:CCFP_CCFPE 0 "cc_register")
+	(if_then_else:CCFP_CCFPE
+	  (match_operand 3 "aarch64_comparison_operator")
+	  (compare:CCFP_CCFPE
+	    (match_operand:GPF 1 "register_operand")
+	    (match_operand:GPF 2 "register_operand"))
+	  (unspec:CCFP_CCFPE
+	    [(match_operand 4 "immediate_operand")]
+	    UNSPEC_NZCV)))]
+  ""
+)
+
+(define_insn "*ccmp<CCFP_CCFPE:mode><GPF:mode>"
+  [(set (match_operand:CCFP_CCFPE 0 "cc_register" "")
 	(if_then_else:CCFP_CCFPE
 	  (match_operator 4 "aarch64_comparison_operator"
-	   [(match_operand 0 "cc_register" "")
+	   [(match_operand 1 "cc_register" "")
 	    (const_int 0)])
 	  (compare:CCFP_CCFPE
 	    (match_operand:GPF 2 "register_operand" "w")
@@ -532,11 +558,24 @@ 
   [(set_attr "type" "fccmp<s>")]
 )
 
-(define_insn "@ccmp<CC_ONLY:mode><GPI:mode>_rev"
-  [(set (match_operand:CC_ONLY 1 "cc_register" "")
+(define_expand "@ccmp<CC_ONLY:mode><GPI:mode>_rev"
+  [(set (match_operand:CC_ONLY 0 "cc_register")
+	(if_then_else:CC_ONLY
+	  (match_operand 3 "aarch64_comparison_operator")
+	  (unspec:CC_ONLY
+	    [(match_operand 4 "immediate_operand")]
+	    UNSPEC_NZCV)
+	  (compare:CC_ONLY
+	    (match_operand:GPI 1 "aarch64_reg_or_zero")
+	    (match_operand:GPI 2 "aarch64_ccmp_operand"))))]
+  ""
+)
+
+(define_insn "*ccmp<CC_ONLY:mode><GPI:mode>_rev"
+  [(set (match_operand:CC_ONLY 0 "cc_register" "")
 	(if_then_else:CC_ONLY
 	  (match_operator 4 "aarch64_comparison_operator"
-	   [(match_operand 0 "cc_register" "")
+	   [(match_operand 1 "cc_register" "")
 	    (const_int 0)])
 	  (unspec:CC_ONLY
 	    [(match_operand 5 "immediate_operand")]
@@ -552,11 +591,24 @@ 
   [(set_attr "type" "alus_sreg,alus_imm,alus_imm")]
 )
 
-(define_insn "@ccmp<CCFP_CCFPE:mode><GPF:mode>_rev"
-  [(set (match_operand:CCFP_CCFPE 1 "cc_register" "")
+(define_expand "@ccmp<CCFP_CCFPE:mode><GPF:mode>_rev"
+  [(set (match_operand:CCFP_CCFPE 0 "cc_register")
+	(if_then_else:CCFP_CCFPE
+	  (match_operand 3 "aarch64_comparison_operator")
+	  (unspec:CCFP_CCFPE
+	    [(match_operand 4 "immediate_operand")]
+	    UNSPEC_NZCV)
+	  (compare:CCFP_CCFPE
+	    (match_operand:GPF 1 "register_operand")
+	    (match_operand:GPF 2 "register_operand"))))]
+  ""
+)
+
+(define_insn "*ccmp<CCFP_CCFPE:mode><GPF:mode>_rev"
+  [(set (match_operand:CCFP_CCFPE 0 "cc_register" "")
 	(if_then_else:CCFP_CCFPE
 	  (match_operator 4 "aarch64_comparison_operator"
-	   [(match_operand 0 "cc_register" "")
+	   [(match_operand 1 "cc_register" "")
 	    (const_int 0)])
 	  (unspec:CCFP_CCFPE
 	    [(match_operand 5 "immediate_operand")]