[2/6] aarch64: Adjust result of aarch64_gen_compare_reg

Message ID	20200319064805.17739-3-richard.henderson@linaro.org
State	New
Headers	show Return-Path: <gcc-patches-bounces@gcc.gnu.org> DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 24AED3940CE5 To: gcc-patches@gcc.gnu.org Subject: [PATCH 2/6] aarch64: Adjust result of aarch64_gen_compare_reg Date: Wed, 18 Mar 2020 23:48:01 -0700 Message-Id: <20200319064805.17739-3-richard.henderson@linaro.org> In-Reply-To: <20200319064805.17739-1-richard.henderson@linaro.org> References: <20200319064805.17739-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: list From: Richard Henderson via Gcc-patches <gcc-patches@gcc.gnu.org> Reply-To: Richard Henderson <richard.henderson@linaro.org> Cc: richard.earnshaw@arm.com, marcus.shawcroft@arm.com Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" <gcc-patches-bounces@gcc.gnu.org>
Series	aarch64: Implement TImode comparisons \| expand [0/6] aarch64: Implement TImode comparisons [1/6] aarch64: Add ucmp__carryinC patterns for all usub__carryinC [2/6] aarch64: Adjust result of aarch64_gen_compare_reg [3/6] aarch64: Accept 0 as first argument to compares [4/6] aarch64: Simplify @ccmp<cc_mode><mode> operands [5/6] aarch64: Improve nzcv argument to ccmp [6/6] aarch64: Implement TImode comparisons

diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index c90de65de12..619357fa210 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -2328,7 +2328,7 @@ emit_set_insn (rtx x, rtx y) } /* X and Y are two things to compare using CODE. Emit the compare insn and - return the rtx for register 0 in the proper mode. */ + return the rtx for the CCmode comparison. */ rtx aarch64_gen_compare_reg (RTX_CODE code, rtx x, rtx y) { @@ -2359,7 +2359,7 @@ aarch64_gen_compare_reg (RTX_CODE code, rtx x, rtx y) cc_reg = gen_rtx_REG (cc_mode, CC_REGNUM); emit_set_insn (cc_reg, gen_rtx_COMPARE (cc_mode, x, y)); } - return cc_reg; + return gen_rtx_fmt_ee (code, VOIDmode, cc_reg, const0_rtx); } /* Similarly, but maybe zero-extend Y if Y_MODE < SImode. */ @@ -2382,7 +2382,7 @@ aarch64_gen_compare_reg_maybe_ze (RTX_CODE code, rtx x, rtx y, cc_mode = CC_SWPmode; cc_reg = gen_rtx_REG (cc_mode, CC_REGNUM); emit_set_insn (cc_reg, t); - return cc_reg; + return gen_rtx_fmt_ee (code, VOIDmode, cc_reg, const0_rtx); } } @@ -18506,7 +18506,8 @@ aarch64_expand_compare_and_swap (rtx operands[]) emit_insn (gen_aarch64_compare_and_swap_lse (mode, rval, mem, newval, mod_s)); - cc_reg = aarch64_gen_compare_reg_maybe_ze (NE, rval, oldval, mode); + x = aarch64_gen_compare_reg_maybe_ze (EQ, rval, oldval, mode); + PUT_MODE (x, SImode); } else if (TARGET_OUTLINE_ATOMICS) { @@ -18517,7 +18518,8 @@ aarch64_expand_compare_and_swap (rtx operands[]) rval = emit_library_call_value (func, NULL_RTX, LCT_NORMAL, r_mode, oldval, mode, newval, mode, XEXP (mem, 0), Pmode); - cc_reg = aarch64_gen_compare_reg_maybe_ze (NE, rval, oldval, mode); + x = aarch64_gen_compare_reg_maybe_ze (EQ, rval, oldval, mode); + PUT_MODE (x, SImode); } else { @@ -18529,13 +18531,13 @@ aarch64_expand_compare_and_swap (rtx operands[]) emit_insn (GEN_FCN (code) (rval, mem, oldval, newval, is_weak, mod_s, mod_f)); cc_reg = gen_rtx_REG (CCmode, CC_REGNUM); + x = gen_rtx_EQ (SImode, cc_reg, const0_rtx); } if (r_mode != mode) rval = gen_lowpart (mode, rval); emit_move_insn (operands[1], rval); - x = gen_rtx_EQ (SImode, cc_reg, const0_rtx); emit_insn (gen_rtx_SET (bval, x)); } @@ -18610,10 +18612,8 @@ aarch64_split_compare_and_swap (rtx operands[]) if (strong_zero_p) x = gen_rtx_NE (VOIDmode, rval, const0_rtx); else - { - rtx cc_reg = aarch64_gen_compare_reg_maybe_ze (NE, rval, oldval, mode); - x = gen_rtx_NE (VOIDmode, cc_reg, const0_rtx); - } + x = aarch64_gen_compare_reg_maybe_ze (NE, rval, oldval, mode); + x = gen_rtx_IF_THEN_ELSE (VOIDmode, x, gen_rtx_LABEL_REF (Pmode, label2), pc_rtx); aarch64_emit_unlikely_jump (gen_rtx_SET (pc_rtx, x)); @@ -18626,8 +18626,7 @@ aarch64_split_compare_and_swap (rtx operands[]) { /* Emit an explicit compare instruction, so that we can correctly track the condition codes. */ - rtx cc_reg = aarch64_gen_compare_reg (NE, scratch, const0_rtx); - x = gen_rtx_NE (GET_MODE (cc_reg), cc_reg, const0_rtx); + x = aarch64_gen_compare_reg (NE, scratch, const0_rtx); } else x = gen_rtx_NE (VOIDmode, scratch, const0_rtx); @@ -18722,8 +18721,7 @@ aarch64_split_atomic_op (enum rtx_code code, rtx old_out, rtx new_out, rtx mem, { /* Emit an explicit compare instruction, so that we can correctly track the condition codes. */ - rtx cc_reg = aarch64_gen_compare_reg (NE, cond, const0_rtx); - x = gen_rtx_NE (GET_MODE (cc_reg), cc_reg, const0_rtx); + x = aarch64_gen_compare_reg (NE, cond, const0_rtx); } else x = gen_rtx_NE (VOIDmode, cond, const0_rtx); diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 24a11fb5040..69e099a2c23 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -4800,10 +4800,8 @@ if (GP_REGNUM_P (REGNO (operands[0])) && GP_REGNUM_P (REGNO (operands[1]))) { - machine_mode mode = SELECT_CC_MODE (<CMP>, operands[1], operands[2]); - rtx cc_reg = aarch64_gen_compare_reg (<CMP>, operands[1], operands[2]); - rtx comparison = gen_rtx_<CMP> (mode, operands[1], operands[2]); - emit_insn (gen_cstoredi_neg (operands[0], comparison, cc_reg)); + rtx cmp = aarch64_gen_compare_reg (<CMP>, operands[1], operands[2]); + emit_insn (gen_cstoredi_neg (operands[0], cmp, XEXP (cmp, 0))); DONE; } /* Otherwise, we expand to a similar pattern which does not @@ -4863,10 +4861,8 @@ if (GP_REGNUM_P (REGNO (operands[0])) && GP_REGNUM_P (REGNO (operands[1]))) { - machine_mode mode = CCmode; - rtx cc_reg = aarch64_gen_compare_reg (<CMP>, operands[1], operands[2]); - rtx comparison = gen_rtx_<CMP> (mode, operands[1], operands[2]); - emit_insn (gen_cstoredi_neg (operands[0], comparison, cc_reg)); + rtx cmp = aarch64_gen_compare_reg (<CMP>, operands[1], operands[2]); + emit_insn (gen_cstoredi_neg (operands[0], cmp, XEXP (cmp, 0))); DONE; } /* Otherwise, we expand to a similar pattern which does not @@ -4936,10 +4932,8 @@ && GP_REGNUM_P (REGNO (operands[1]))) { rtx and_tree = gen_rtx_AND (DImode, operands[1], operands[2]); - machine_mode mode = SELECT_CC_MODE (NE, and_tree, const0_rtx); - rtx cc_reg = aarch64_gen_compare_reg (NE, and_tree, const0_rtx); - rtx comparison = gen_rtx_NE (mode, and_tree, const0_rtx); - emit_insn (gen_cstoredi_neg (operands[0], comparison, cc_reg)); + rtx cmp = aarch64_gen_compare_reg (NE, and_tree, const0_rtx); + emit_insn (gen_cstoredi_neg (operands[0], cmp, XEXP (cmp, 0))); DONE; } /* Otherwise, we expand to a similar pattern which does not diff --git a/gcc/config/aarch64/aarch64-speculation.cc b/gcc/config/aarch64/aarch64-speculation.cc index f490b64ae61..87d5964871b 100644 --- a/gcc/config/aarch64/aarch64-speculation.cc +++ b/gcc/config/aarch64/aarch64-speculation.cc @@ -162,9 +162,8 @@ aarch64_speculation_establish_tracker () rtx sp = gen_rtx_REG (DImode, SP_REGNUM); rtx tracker = gen_rtx_REG (DImode, SPECULATION_TRACKER_REGNUM); start_sequence (); - rtx cc = aarch64_gen_compare_reg (EQ, sp, const0_rtx); - emit_insn (gen_cstoredi_neg (tracker, - gen_rtx_NE (CCmode, cc, const0_rtx), cc)); + rtx x = aarch64_gen_compare_reg (NE, sp, const0_rtx); + emit_insn (gen_cstoredi_neg (tracker, x, XEXP (x, 0))); rtx_insn *seq = get_insns (); end_sequence (); return seq; diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index fcc1ddafaec..29dfd6df30c 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -464,12 +464,12 @@ (label_ref (match_operand 3 "" "")) (pc)))] "" - " - operands[1] = aarch64_gen_compare_reg (GET_CODE (operands[0]), operands[1], +{ + operands[0] = aarch64_gen_compare_reg (GET_CODE (operands[0]), operands[1], operands[2]); + operands[1] = XEXP (operands[0], 0); operands[2] = const0_rtx; - " -) +}) (define_expand "cbranch<mode>4" [(set (pc) (if_then_else (match_operator 0 "aarch64_comparison_operator" @@ -478,12 +478,12 @@ (label_ref (match_operand 3 "" "")) (pc)))] "" - " - operands[1] = aarch64_gen_compare_reg (GET_CODE (operands[0]), operands[1], +{ + operands[0] = aarch64_gen_compare_reg (GET_CODE (operands[0]), operands[1], operands[2]); + operands[1] = XEXP (operands[0], 0); operands[2] = const0_rtx; - " -) +}) (define_expand "cbranchcc4" [(set (pc) (if_then_else @@ -598,9 +598,8 @@ if (val == 2) { rtx masked = gen_reg_rtx (<MODE>mode); - rtx ccreg = aarch64_gen_compare_reg (LT, operands[1], const0_rtx); + rtx x = aarch64_gen_compare_reg (LT, operands[1], const0_rtx); emit_insn (gen_and<mode>3 (masked, operands[1], mask)); - rtx x = gen_rtx_LT (VOIDmode, ccreg, const0_rtx); emit_insn (gen_csneg3<mode>_insn (operands[0], x, masked, masked)); DONE; } @@ -3671,8 +3670,7 @@ (match_operand:GPI 1 "register_operand")] "" { - rtx ccreg = aarch64_gen_compare_reg (LT, operands[1], const0_rtx); - rtx x = gen_rtx_LT (VOIDmode, ccreg, const0_rtx); + rtx x = aarch64_gen_compare_reg (LT, operands[1], const0_rtx); emit_insn (gen_csneg3<mode>_insn (operands[0], x, operands[1], operands[1])); DONE; } @@ -4086,12 +4084,13 @@ [(match_operand:GPI 2 "register_operand") (match_operand:GPI 3 "aarch64_plus_operand")]))] "" - " - operands[2] = aarch64_gen_compare_reg (GET_CODE (operands[1]), operands[2], - operands[3]); +{ + operands[1] = aarch64_gen_compare_reg (GET_CODE (operands[1]), operands[2], + operands[3]); + PUT_MODE (operands[1], SImode); + operands[2] = XEXP (operands[1], 0); operands[3] = const0_rtx; - " -) +}) (define_expand "cstorecc4" [(set (match_operand:SI 0 "register_operand") @@ -4099,11 +4098,10 @@ [(match_operand 2 "cc_register") (match_operand 3 "const0_operand")]))] "" -"{ +{ emit_insn (gen_rtx_SET (operands[0], operands[1])); DONE; -}") - +}) (define_expand "cstore<mode>4" [(set (match_operand:SI 0 "register_operand") @@ -4111,12 +4109,13 @@ [(match_operand:GPF 2 "register_operand") (match_operand:GPF 3 "aarch64_fp_compare_operand")]))] "" - " - operands[2] = aarch64_gen_compare_reg (GET_CODE (operands[1]), operands[2], - operands[3]); +{ + operands[1] = aarch64_gen_compare_reg (GET_CODE (operands[1]), operands[2], + operands[3]); + PUT_MODE (operands[1], SImode); + operands[2] = XEXP (operands[1], 0); operands[3] = const0_rtx; - " -) +}) (define_insn "aarch64_cstore<mode>" [(set (match_operand:ALLI 0 "register_operand" "=r") @@ -4202,12 +4201,12 @@ (match_operand:GPI 4 "register_operand") (match_operand:GPI 5 "register_operand")))] "" - " - operands[2] = aarch64_gen_compare_reg (GET_CODE (operands[1]), operands[2], - operands[3]); +{ + operands[1] = aarch64_gen_compare_reg (GET_CODE (operands[1]), operands[2], + operands[3]); + operands[2] = XEXP (operands[1], 0); operands[3] = const0_rtx; - " -) +}) (define_expand "cmov<mode>6" [(set (match_operand:GPF 0 "register_operand") @@ -4218,12 +4217,12 @@ (match_operand:GPF 4 "register_operand") (match_operand:GPF 5 "register_operand")))] "" - " - operands[2] = aarch64_gen_compare_reg (GET_CODE (operands[1]), operands[2], - operands[3]); +{ + operands[1] = aarch64_gen_compare_reg (GET_CODE (operands[1]), operands[2], + operands[3]); + operands[2] = XEXP (operands[1], 0); operands[3] = const0_rtx; - " -) +}) (define_insn "*cmov<mode>_insn" [(set (match_operand:ALLI 0 "register_operand" "=r,r,r,r,r,r,r") @@ -4300,15 +4299,13 @@ (match_operand:ALLI 3 "register_operand")))] "" { - rtx ccreg; enum rtx_code code = GET_CODE (operands[1]); if (code == UNEQ || code == LTGT) FAIL; - ccreg = aarch64_gen_compare_reg (code, XEXP (operands[1], 0), - XEXP (operands[1], 1)); - operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx); + operands[1] = aarch64_gen_compare_reg (code, XEXP (operands[1], 0), + XEXP (operands[1], 1)); } ) @@ -4319,15 +4316,13 @@ (match_operand:GPF 3 "register_operand")))] "" { - rtx ccreg; enum rtx_code code = GET_CODE (operands[1]); if (code == UNEQ || code == LTGT) FAIL; - ccreg = aarch64_gen_compare_reg (code, XEXP (operands[1], 0), - XEXP (operands[1], 1)); - operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx); + operands[1] = aarch64_gen_compare_reg (code, XEXP (operands[1], 0), + XEXP (operands[1], 1)); } ) @@ -4338,15 +4333,13 @@ (match_operand:GPF 3 "register_operand")))] "" { - rtx ccreg; enum rtx_code code = GET_CODE (operands[1]); if (code == UNEQ || code == LTGT) FAIL; - ccreg = aarch64_gen_compare_reg (code, XEXP (operands[1], 0), - XEXP (operands[1], 1)); - operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx); + operands[1] = aarch64_gen_compare_reg (code, XEXP (operands[1], 0), + XEXP (operands[1], 1)); } ) @@ -4357,15 +4350,13 @@ (match_operand:GPI 3 "register_operand")))] "" { - rtx ccreg; enum rtx_code code = GET_CODE (operands[1]); if (code == UNEQ || code == LTGT) FAIL; - ccreg = aarch64_gen_compare_reg (code, XEXP (operands[1], 0), - XEXP (operands[1], 1)); - operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx); + operands[1] = aarch64_gen_compare_reg (code, XEXP (operands[1], 0), + XEXP (operands[1], 1)); } ) @@ -4874,8 +4865,7 @@ (match_operand:GPI 1 "register_operand")] "" { - rtx ccreg = aarch64_gen_compare_reg (EQ, operands[1], const0_rtx); - rtx x = gen_rtx_NE (VOIDmode, ccreg, const0_rtx); + rtx x = aarch64_gen_compare_reg (NE, operands[1], const0_rtx); emit_insn (gen_rbit<mode>2 (operands[0], operands[1])); emit_insn (gen_clz<mode>2 (operands[0], operands[0]));

[2/6] aarch64: Adjust result of aarch64_gen_compare_reg

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