From patchwork Mon Feb 3 11:38:29 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Zissulescu Ianculescu X-Patchwork-Id: 1232724 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-518746-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha1 header.s=default header.b=P8AFYAu4; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=KGlIsoq3; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 48B5SW0dW0z9sPK for ; Mon, 3 Feb 2020 22:38:50 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:mime-version :content-transfer-encoding; q=dns; s=default; b=UUeUV334+0lKQV4T 9Y5dXGqUbqaSwJcRo7f9hyegRhpjmsYUj/gkotv4Stzvr4w4XanzrvM/1KIL8tIU a5CD9XaeTzcopQ0V4xpSLUDYnPip961YOFL28Ol7SLUGlpkNkJU/8pVjpp5CaSwz tpX0y7bWZW3RNapITI1qFE3+DwA= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:mime-version :content-transfer-encoding; s=default; bh=Xvcg7jYup9nitrRadmcQW8 qSW8M=; b=P8AFYAu4YI+Neqms4z7klgpgZgmxvR2l4WTtjcQMmxOLf+y85qzGih o2IL1bQFrimdoiZ+JCk6YG5ssO5Sa9QNaeTX6XsEoiHlCyd7fJLN92ALQtOhCZoI sXu0GykIFd4hwpuFjlZetW1XyrcNGOG75ciCiQKg3lGvL3SzxcR1c= Received: (qmail 59228 invoked by alias); 3 Feb 2020 11:38:43 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 59220 invoked by uid 89); 3 Feb 2020 11:38:43 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-15.3 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.1 spammy=mbig-endian, mbigendian, emit_move_insn, rr X-HELO: mail-wm1-f68.google.com Received: from mail-wm1-f68.google.com (HELO mail-wm1-f68.google.com) (209.85.128.68) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 03 Feb 2020 11:38:41 +0000 Received: by mail-wm1-f68.google.com with SMTP id s10so15469692wmh.3 for ; Mon, 03 Feb 2020 03:38:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=DyU2jiGK3muEAOjqGyp7wBBV9bDmrUlN3/2onUUy0ew=; b=KGlIsoq3coeYV4jwGWIG7av0Ucw0cOkJz1dkLPLNWOWojot/z1/H1Bj45FekypDpVY DzmhBSs2bxnldH2D37zTin8D0jDAmaJPQQA+IMbWQiDI/9uiINhKETaDJJqL4mUbA6ym QdFe5DWdjppxN1bV/7hnJD6tmNo628H1GREnB7zzPwXn8mVpJnI34GYAuoI/PbAt2NDV UXGsKxdACnQZmNKskW/LwXcF1iIorRCl+3pMuQC7Z8K0c4c5VBFcEjYBO1ZJ9rZJvweU WbR01DlNRYrfX1osDWkQqe2EFD7KDnOhwizGFaETpBbIfL5vk24Zygd1iu/2+8r93nio GVpA== Received: from engy.ddns.hightechcampus.nl ([80.255.245.234]) by smtp.gmail.com with ESMTPSA id 5sm22030481wrc.75.2020.02.03.03.38.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Feb 2020 03:38:38 -0800 (PST) From: Claudiu Zissulescu To: gcc-patches@gcc.gnu.org Cc: andrew.burgess@embecosm.com, fbedard@synopsys.com, law@redhat.com Subject: [PATCH 1/4] [ARC] Update mlo/mhi handling when big-endian CPU. Date: Mon, 3 Feb 2020 12:38:29 +0100 Message-Id: <20200203113832.20270-1-claziss@gmail.com> MIME-Version: 1.0 X-IsSubscribed: yes The ARC 600 MUL64 instructions are using mlo/mhi registers to pass the 64-bit result. However, the mlo/mhi registers are not swapping depending on endianess. Update multiplication patterns to reflect this fact. gcc/ xxxx-xx-xx Claudiu Zissulescu * config/arc/arc.md (mulsidi_600): Correctly select mlo/mhi registers. (umulsidi_600): Likewise. testsuite/ xxxx-xx-xx Claudiu Zissulescu Petro Karashchenko * estsuite/gcc.target/arc/mul64-1.c: New test. --- gcc/config/arc/arc.md | 50 ++++++++++++++++---------- gcc/testsuite/gcc.target/arc/mul64-1.c | 23 ++++++++++++ 2 files changed, 55 insertions(+), 18 deletions(-) create mode 100644 gcc/testsuite/gcc.target/arc/mul64-1.c diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md index 9a96440025f..f19f2c32641 100644 --- a/gcc/config/arc/arc.md +++ b/gcc/config/arc/arc.md @@ -2288,19 +2288,26 @@ archs4x, archs4xd" (set_attr "cond" "canuse,canuse,canuse_limm,canuse")]) (define_insn_and_split "mulsidi_600" - [(set (match_operand:DI 0 "register_operand" "=c, c,c, c") - (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "%Rcq#q, c,c, c")) - (sign_extend:DI (match_operand:SI 2 "nonmemory_operand" "Rcq#q,cL,L,C32")))) - (clobber (reg:DI MUL64_OUT_REG))] + [(set (match_operand:DI 0 "register_operand" "=r,r, r") + (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "%r,r, r")) + (sign_extend:DI (match_operand:SI 2 "nonmemory_operand" "rL,L,C32")))) + (clobber (reg:DI R58_REG))] "TARGET_MUL64_SET" "#" - "TARGET_MUL64_SET" + "TARGET_MUL64_SET && reload_completed" [(const_int 0)] - "emit_insn (gen_mul64 (operands[1], operands[2])); - emit_move_insn (operands[0], gen_rtx_REG (DImode, MUL64_OUT_REG)); - DONE;" + { + int hi = !TARGET_BIG_ENDIAN; + int lo = !hi; + rtx lr = operand_subword (operands[0], lo, 0, DImode); + rtx hr = operand_subword (operands[0], hi, 0, DImode); + emit_insn (gen_mul64 (operands[1], operands[2])); + emit_move_insn (lr, gen_rtx_REG (SImode, R58_REG)); + emit_move_insn (hr, gen_rtx_REG (SImode, R59_REG)); + DONE; + } [(set_attr "type" "multi") - (set_attr "length" "8")]) + (set_attr "length" "4,4,8")]) (define_insn "mul64" [(set (reg:DI MUL64_OUT_REG) @@ -2316,19 +2323,26 @@ archs4x, archs4xd" (set_attr "cond" "canuse,canuse,canuse_limm,canuse")]) (define_insn_and_split "umulsidi_600" - [(set (match_operand:DI 0 "register_operand" "=c,c, c") - (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%c,c, c")) - (sign_extend:DI (match_operand:SI 2 "nonmemory_operand" "cL,L,C32")))) - (clobber (reg:DI MUL64_OUT_REG))] + [(set (match_operand:DI 0 "register_operand" "=r,r, r") + (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%r,r, r")) + (zero_extend:DI (match_operand:SI 2 "nonmemory_operand" "rL,L,C32")))) + (clobber (reg:DI R58_REG))] "TARGET_MUL64_SET" "#" - "TARGET_MUL64_SET" + "TARGET_MUL64_SET && reload_completed" [(const_int 0)] - "emit_insn (gen_mulu64 (operands[1], operands[2])); - emit_move_insn (operands[0], gen_rtx_REG (DImode, MUL64_OUT_REG)); - DONE;" + { + int hi = !TARGET_BIG_ENDIAN; + int lo = !hi; + rtx lr = operand_subword (operands[0], lo, 0, DImode); + rtx hr = operand_subword (operands[0], hi, 0, DImode); + emit_insn (gen_mulu64 (operands[1], operands[2])); + emit_move_insn (lr, gen_rtx_REG (SImode, R58_REG)); + emit_move_insn (hr, gen_rtx_REG (SImode, R59_REG)); + DONE; + } [(set_attr "type" "umulti") - (set_attr "length" "8")]) + (set_attr "length" "4,4,8")]) (define_insn "mulu64" [(set (reg:DI MUL64_OUT_REG) diff --git a/gcc/testsuite/gcc.target/arc/mul64-1.c b/gcc/testsuite/gcc.target/arc/mul64-1.c new file mode 100644 index 00000000000..2543fc33d3f --- /dev/null +++ b/gcc/testsuite/gcc.target/arc/mul64-1.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-skip-if "MUL64 is ARC600 extension." { ! { clmcpu } } } */ +/* { dg-options "-O2 -mmul64 -mbig-endian -mcpu=arc600" } */ + +/* Check if mlo/mhi registers are correctly layout when we compile for + a big-endian CPU. */ + +#include + +uint32_t foo (uint32_t x) +{ + return x % 1000; +} + +int32_t bar (int32_t x) +{ + return x % 1000; +} + +/* { dg-final { scan-assembler-times "\\s+mul64\\s+" 3 } } */ +/* { dg-final { scan-assembler-times "\\s+mulu64\\s+" 1 } } */ +/* { dg-final { scan-assembler-times "r\[0-9\]+,mhi" 2 } } */ +/* { dg-final { scan-assembler-times "r\[0-9\]+,mlo" 2 } } */