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V11 patch #10 of 15, Make sure we don't generate pre-modify prefixed insns with -mcpu=future

Message ID 20191221001418.GJ28993@ibm-toto.the-meissners.org
State New
Headers show
Series V11 patch #10 of 15, Make sure we don't generate pre-modify prefixed insns with -mcpu=future | expand

Commit Message

Michael Meissner Dec. 21, 2019, 12:14 a.m. UTC 
This is V10 patch #12.  It adds a test to make sure we don't generate a
prefixed instruction with PRE_INC, PRE_DEC, or PRE_MODIFY.
https://gcc.gnu.org/ml/gcc-patches/2019-12/msg00846.html

This test passes when I run it.  Can I check this into the trunk?

2019-12-20  Michael Meissner  <meissner@linux.ibm.com>

	* gcc.target/powerpc/prefix-no-premodify.c: Make sure we do not
	generate the non-existent PLWZU instruction if -mcpu=future.
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Patch

Index: gcc/testsuite/gcc.target/powerpc/prefix-no-premodify.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/prefix-no-premodify.c	(revision 279259)
+++ gcc/testsuite/gcc.target/powerpc/prefix-no-premodify.c	(working copy)
@@ -0,0 +1,50 @@ 
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_prefixed_addr } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Make sure that we don't generate a prefixed form of the load and store with
+   update instructions (i.e. instead of generating LWZU we have to generate
+   PLWZ plus a PADDI).  */
+
+#ifndef SIZE
+#define SIZE 50000
+#endif
+
+struct foo {
+  unsigned int field;
+  char pad[SIZE];
+};
+
+struct foo *inc_load (struct foo *p, unsigned int *q)
+{
+  *q = (++p)->field;	/* PLWZ, PADDI, STW.  */
+  return p;
+}
+
+struct foo *dec_load (struct foo *p, unsigned int *q)
+{
+  *q = (--p)->field;	/* PLWZ, PADDI, STW.  */
+  return p;
+}
+
+struct foo *inc_store (struct foo *p, unsigned int *q)
+{
+  (++p)->field = *q;	/* LWZ, PADDI, PSTW.  */
+  return p;
+}
+
+struct foo *dec_store (struct foo *p, unsigned int *q)
+{
+  (--p)->field = *q;	/* LWZ, PADDI, PSTW.  */
+  return p;
+}
+
+/* { dg-final { scan-assembler-times {\mlwz\M}    2 } } */
+/* { dg-final { scan-assembler-times {\mstw\M}    2 } } */
+/* { dg-final { scan-assembler-times {\mpaddi\M}  4 } } */
+/* { dg-final { scan-assembler-times {\mplwz\M}   2 } } */
+/* { dg-final { scan-assembler-times {\mpstw\M}   2 } } */
+/* { dg-final { scan-assembler-not   {\mplwzu\M}    } } */
+/* { dg-final { scan-assembler-not   {\mpstwu\M}    } } */
+/* { dg-final { scan-assembler-not   {\maddis\M}    } } */
+/* { dg-final { scan-assembler-not   {\maddi\M}     } } */