diff mbox series

V11 patch #4 of 15, Update 'Q' constraint documentation.

Message ID 20191220234930.GD28993@ibm-toto.the-meissners.org
State New
Headers show
Series V11 patch #4 of 15, Update 'Q' constraint documentation. | expand

Commit Message

Michael Meissner Dec. 20, 2019, 11:49 p.m. UTC 
In doing V11 patch #3, I noticed that the documentation for the 'Q' was
misleading.  This patch updates the documentation.  Can I check this patch into
the trunk?

2019-12-20  Michael Meissner  <meissner@linux.ibm.com>

	* config/rs6000/constraints.md (Q constraint): Update
	documentation.
	* doc/md.tet (PowerPC constraints): Update 'Q' constraint
	documentation.

Comments

Segher Boessenkool Dec. 22, 2019, 5:49 p.m. UTC | #1 
On Fri, Dec 20, 2019 at 06:49:30PM -0500, Michael Meissner wrote:
> In doing V11 patch #3, I noticed that the documentation for the 'Q' was
> misleading.

It originally was used just for lswi/stswi, which can access up to the
first 32 bytes of storage pointed to by the register.  But yes, the
current comment is confusing.

> 	* config/rs6000/constraints.md (Q constraint): Update
> 	documentation.
> 	* doc/md.tet (PowerPC constraints): Update 'Q' constraint
> 	documentation.

"md.tet"?  That's an interesting typo :-)

>  (define_memory_constraint "Q"
> -  "Memory operand that is an offset from a register (it is usually better
> -to use @samp{m} or @samp{es} in @code{asm} statements)"
> +  "A memory operand whose address which uses a single register with no offset."

Arm has

(define_memory_constraint "Q"
 "@internal
  An address that is a single base register."
 (and (match_code "mem")
      (match_test "REG_P (XEXP (op, 0))")))

which is more correct for us (the register cannot be r0!)

But it is not an address.

Maybe "A memory operand addressed by just a base register." ?

Okay for trunk like that.  Thanks!


Segher
Michael Meissner Jan. 7, 2020, 1:44 a.m. UTC | #2 
On Sun, Dec 22, 2019 at 11:49:19AM -0600, Segher Boessenkool wrote:
> On Fri, Dec 20, 2019 at 06:49:30PM -0500, Michael Meissner wrote:
> > In doing V11 patch #3, I noticed that the documentation for the 'Q' was
> > misleading.
> 
> It originally was used just for lswi/stswi, which can access up to the
> first 32 bytes of storage pointed to by the register.  But yes, the
> current comment is confusing.
> 
> > 	* config/rs6000/constraints.md (Q constraint): Update
> > 	documentation.
> > 	* doc/md.tet (PowerPC constraints): Update 'Q' constraint
> > 	documentation.
> 
> "md.tet"?  That's an interesting typo :-)
> 
> >  (define_memory_constraint "Q"
> > -  "Memory operand that is an offset from a register (it is usually better
> > -to use @samp{m} or @samp{es} in @code{asm} statements)"
> > +  "A memory operand whose address which uses a single register with no offset."
> 
> Arm has
> 
> (define_memory_constraint "Q"
>  "@internal
>   An address that is a single base register."
>  (and (match_code "mem")
>       (match_test "REG_P (XEXP (op, 0))")))
> 
> which is more correct for us (the register cannot be r0!)
> 
> But it is not an address.
> 
> Maybe "A memory operand addressed by just a base register." ?
> 
> Okay for trunk like that.  Thanks!

This is the patch I committed (subversion ids 279939 and 279940).

2020-01-06  Michael Meissner  <meissner@linux.ibm.com>

	* config/rs6000/constraints.md (Q constraint): Update
	documentation.
	* doc/md.texi (RS/6000 constraints): Update 'Q' cosntraint
	documentation.

Index: gcc/config/rs6000/constraints.md
===================================================================
--- gcc/config/rs6000/constraints.md	(revision 279910)
+++ gcc/config/rs6000/constraints.md	(working copy)
@@ -211,8 +211,7 @@ several times, or that might not access
        (match_test "GET_RTX_CLASS (GET_CODE (XEXP (op, 0))) != RTX_AUTOINC")))
 
 (define_memory_constraint "Q"
-  "Memory operand that is an offset from a register (it is usually better
-to use @samp{m} or @samp{es} in @code{asm} statements)"
+  "A memory operand addressed by just a base register."
   (and (match_code "mem")
        (match_test "REG_P (XEXP (op, 0))")))
 
Index: gcc/doc/md.texi
===================================================================
--- gcc/doc/md.texi	(revision 279910)
+++ gcc/doc/md.texi	(working copy)
@@ -3381,8 +3381,7 @@ allowed when @samp{<} or @samp{>} is use
 as @samp{m} without @samp{<} and @samp{>}.
 
 @item Q
-Memory operand that is an offset from a register (it is usually better
-to use @samp{m} or @samp{es} in @code{asm} statements)
+A memory operand addressed by just a base register.
 
 @item Z
 Memory operand that is an indexed or indirect from a register (it is
diff mbox series

Patch

Index: gcc/config/rs6000/constraints.md
===================================================================
--- gcc/config/rs6000/constraints.md	(revision 279547)
+++ gcc/config/rs6000/constraints.md	(working copy)
@@ -211,8 +211,7 @@  several times, or that might not access
        (match_test "GET_RTX_CLASS (GET_CODE (XEXP (op, 0))) != RTX_AUTOINC")))
 
 (define_memory_constraint "Q"
-  "Memory operand that is an offset from a register (it is usually better
-to use @samp{m} or @samp{es} in @code{asm} statements)"
+  "A memory operand whose address which uses a single register with no offset."
   (and (match_code "mem")
        (match_test "REG_P (XEXP (op, 0))")))
 
Index: gcc/doc/md.texi
===================================================================
--- gcc/doc/md.texi	(revision 279547)
+++ gcc/doc/md.texi	(working copy)
@@ -3381,8 +3381,7 @@  allowed when @samp{<} or @samp{>} is use
 as @samp{m} without @samp{<} and @samp{>}.
 
 @item Q
-Memory operand that is an offset from a register (it is usually better
-to use @samp{m} or @samp{es} in @code{asm} statements)
+A memory operand whose address which uses a single register with no offset.
 
 @item Z
 Memory operand that is an indexed or indirect from a register (it is