diff mbox series

[Committed] Fix PR92950: Wrong code emitted for movv1qi

Message ID 20191216080359.31206-1-krebbel@linux.ibm.com
State New
Headers show
Series [Committed] Fix PR92950: Wrong code emitted for movv1qi | expand

Commit Message

Andreas Krebbel Dec. 16, 2019, 8:03 a.m. UTC 
The backend emits 16 bit memory loads for single element character
vector.  As a result the character will not be right justified in the
GPR.

gcc/ChangeLog:

2019-12-16  Andreas Krebbel  <krebbel@linux.ibm.com>

	PR target/92950
	* config/s390/vector.md ("mov<mode>" for V_8): Replace lh, lhy,
	and lhrl with llc.

gcc/testsuite/ChangeLog:

2019-12-16  Andreas Krebbel  <krebbel@linux.ibm.com>

	PR target/92950
	* gcc.target/s390/vector/pr92950.c: New test.
---
 gcc/config/s390/vector.md                     | 12 ++++------
 .../gcc.target/s390/vector/pr92950.c          | 24 +++++++++++++++++++
 2 files changed, 29 insertions(+), 7 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/s390/vector/pr92950.c
diff mbox series

Patch

diff --git a/gcc/config/s390/vector.md b/gcc/config/s390/vector.md
index d40e310f9e7..1e591ba31b6 100644
--- a/gcc/config/s390/vector.md
+++ b/gcc/config/s390/vector.md
@@ -291,9 +291,9 @@ 
 ; However, this would probably be slower.
 
 (define_insn "mov<mode>"
-  [(set (match_operand:V_8 0 "nonimmediate_operand" "=v,v,d,v,R,  v,  v,  v,  v,d,  Q,  S,  Q,  S,  d,  d,d,d,d,R,T")
-        (match_operand:V_8 1 "general_operand"      " v,d,v,R,v,j00,jm1,jyy,jxx,d,j00,j00,jm1,jm1,j00,jm1,R,T,b,d,d"))]
-  ""
+  [(set (match_operand:V_8 0 "nonimmediate_operand" "=v,v,d,v,R,  v,  v,  v,  v,d,  Q,  S,  Q,  S,  d,  d,d,R,T")
+        (match_operand:V_8 1 "general_operand"      " v,d,v,R,v,j00,jm1,jyy,jxx,d,j00,j00,jm1,jm1,j00,jm1,T,d,d"))]
+  "TARGET_VX"
   "@
    vlr\t%v0,%v1
    vlvgb\t%v0,%1,0
@@ -311,12 +311,10 @@ 
    mviy\t%0,-1
    lhi\t%0,0
    lhi\t%0,-1
-   lh\t%0,%1
-   lhy\t%0,%1
-   lhrl\t%0,%1
+   llc\t%0,%1
    stc\t%1,%0
    stcy\t%1,%0"
-  [(set_attr "op_type"      "VRR,VRS,VRS,VRX,VRX,VRI,VRI,VRI,VRI,RR,SI,SIY,SI,SIY,RI,RI,RX,RXY,RIL,RX,RXY")])
+  [(set_attr "op_type"      "VRR,VRS,VRS,VRX,VRX,VRI,VRI,VRI,VRI,RR,SI,SIY,SI,SIY,RI,RI,RXY,RX,RXY")])
 
 (define_insn "mov<mode>"
   [(set (match_operand:V_16 0 "nonimmediate_operand" "=v,v,d,v,R,  v,  v,  v,  v,d,  Q,  Q,  d,  d,d,d,d,R,T,b")
diff --git a/gcc/testsuite/gcc.target/s390/vector/pr92950.c b/gcc/testsuite/gcc.target/s390/vector/pr92950.c
new file mode 100644
index 00000000000..9c7ed127e61
--- /dev/null
+++ b/gcc/testsuite/gcc.target/s390/vector/pr92950.c
@@ -0,0 +1,24 @@ 
+/* { dg-do run } */
+/* { dg-options "-O3 -mzarch -march=z13 --save-temps" } */
+
+struct a {
+  int b;
+  char c;
+};
+struct a d = {1, 16};
+struct a *e = &d;
+
+int f = 0;
+
+int main() {
+  struct a g = {0, 0 };
+  f = 0;
+
+  for (; f <= 1; f++) {
+    g = d;
+    *e = g;
+  }
+
+  if (d.c != 16)
+    __builtin_abort();
+}