From patchwork Tue Oct 8 10:39:57 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jozef Lawrynowicz X-Patchwork-Id: 1173175 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-510454-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=mittosystems.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="fGlBPcWF"; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=mittosystems.com header.i=@mittosystems.com header.b="NYt6mQAY"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46nYlL6m5Bz9sN1 for ; Tue, 8 Oct 2019 21:40:13 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:subject:message-id:in-reply-to:references:mime-version :content-type; q=dns; s=default; b=FyW5YgYH6p1AhW9SAKTJNGWOafAaA i9X9aNP5vlk77wEl6hb5edvR59GsLmkEL6r6o0SszcydbFJ9oUgIUsLTJZ+UqXrL /3Ni12rMqu+XjQf8VgkB0zCjOBf9ttGRNVmsjGlDf067o2HkV8hexwjXJOq3M6em CZCPHOHz/C4Jts= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:subject:message-id:in-reply-to:references:mime-version :content-type; s=default; bh=ddI6YYeFgtqIwl8Iwo11QMf/ChA=; b=fGl BPcWF7KIQKQlxC9CzomR6gKcnxjatPyu+/uJP+D6r8UHn6m371SbD1PhFYGfVoJb FYxzDAQmo7Ew4BlQbuL6GgR6M21JJa4XyrtUHno6hnjt40ZADrEUjdmgCF3O2Udj G1PHJ/n3MnmvdkO0vGkf2NgRt/TkOpwRLi9dh+GM= Received: (qmail 100249 invoked by alias); 8 Oct 2019 10:40:04 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 100082 invoked by uid 89); 8 Oct 2019 10:40:04 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.1 spammy=Below X-HELO: mail-wm1-f54.google.com Received: from mail-wm1-f54.google.com (HELO mail-wm1-f54.google.com) (209.85.128.54) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 08 Oct 2019 10:40:02 +0000 Received: by mail-wm1-f54.google.com with SMTP id 3so2581579wmi.3 for ; Tue, 08 Oct 2019 03:40:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mittosystems.com; s=google; h=date:from:to:subject:message-id:in-reply-to:references:mime-version; bh=TO8+D3wTuCVj8GKXxS7oDz0gMnF7QBQq7cKqXfZMSt8=; b=NYt6mQAYm8PJYjCOim4K3iGABFAX12zTwFkEaOQyS9EnW5RUo7knaYThaxXyxIM7Tk SzpFgVd69zAVaegBujOnBIIgamuDE/G7jm6mGlWGqXTpI7GQIAdYEwE1I5uGf60cNswv MUD+KWOR8iStJvgKy/KYNmsS9zre1LraROpdBpYPm1WqB3JYZdWzQjsdNgatSqrSBF6/ QCqyGo3F8TLQkMcPBml7waStyukGVLfbimZqVPswUh870SeBju4cuoZjKmZm71g8LpD/ FeMrT6xsIa9YZrjCUuwRGidWjHlsqXc7cL7kCraTvZnma0WSoggzaNh+wVoU3PeEMsZC 2k9A== Received: from jozef-kubuntu ([2a01:4b00:87fd:900:dcf5:b2e3:466f:8152]) by smtp.gmail.com with ESMTPSA id t4sm16826016wrm.13.2019.10.08.03.39.59 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 08 Oct 2019 03:39:59 -0700 (PDT) Date: Tue, 8 Oct 2019 11:39:57 +0100 From: Jozef Lawrynowicz To: "gcc-patches@gcc.gnu.org" Subject: [PATCH 2/2][MSP430] Optimize zero_extend insns and PSImode pointer manipulation Message-ID: <20191008113957.054ec793@jozef-kubuntu> In-Reply-To: <20191008113450.5b6fa184@jozef-kubuntu> References: <20191008113450.5b6fa184@jozef-kubuntu> MIME-Version: 1.0 X-IsSubscribed: yes This patch has the functional changes to optimize zero_extend insns and pointer manipulation in the large memory model. From f8156e115c4743ce94a86835ffa5601b6d28a555 Mon Sep 17 00:00:00 2001 From: Jozef Lawrynowicz Date: Mon, 7 Oct 2019 11:44:16 +0100 Subject: [PATCH 2/2] MSP430: PSImode pointer manipulation and zero extend insn optimizations gcc/ChangeLog: 2019-10-08 Jozef Lawrynowicz * config/msp430/msp430.md (movqipsi): New. (zero_extendqipsi2): New. (zero_extendqisi2): Optimize case where src register and base dst register are the same. (zero_extendhipsi2): Don't use 430X insn for rYs->r case. (zero_extendpsisi2): Optimize r->m case. Add unnamed insn patterns to catch insns combine searches for when optimizing pointer manipulation. --- gcc/config/msp430/msp430.md | 135 +++++++++++++++++++++++++++++++----- 1 file changed, 117 insertions(+), 18 deletions(-) diff --git a/gcc/config/msp430/msp430.md b/gcc/config/msp430/msp430.md index 2e8e8326232..cb0b3f16dc5 100644 --- a/gcc/config/msp430/msp430.md +++ b/gcc/config/msp430/msp430.md @@ -182,6 +182,15 @@ MOV%X1.B\t%1, %0" ) +(define_insn "movqipsi" + [(set (match_operand:PSI 0 "register_operand" "=r,r") + (zero_extend:PSI (match_operand:QI 1 "general_operand" "rYs,m")))] + "msp430x" + "@ + MOV.B\t%1, %0 + MOV%X1.B\t%1, %0" +) + (define_insn "movqi_topbyte" [(set (match_operand:QI 0 "msp430_general_dst_operand" "=r") (subreg:QI (match_operand:PSI 1 "msp430_general_operand" "r") 2))] @@ -553,6 +562,16 @@ SXT%X0\t%0" ) +;; ------------------------ +;; ZERO EXTEND INSTRUCTIONS +;; Byte-writes to registers clear bits 19:8 +;; * Byte-writes to memory do not affect bits 15:8 +;; Word-writes to registers clear bits 19:16 +;; PSImode writes to memory clear bits 16:4 of the second memory word +;; We define all possible insns since that results in better code than if +;; they are inferred. +;; ------------------------ + (define_insn "zero_extendqihi2" [(set (match_operand:HI 0 "msp430_general_dst_operand" "=rYs,r,r,m") (zero_extend:HI (match_operand:QI 1 "msp430_general_operand" "0,rYs,m,0")))] @@ -564,19 +583,31 @@ AND%X0\t#0xff, %0" ) +(define_insn "zero_extendqipsi2" + [(set (match_operand:PSI 0 "register_operand" "=r,r") + (zero_extend:PSI (match_operand:QI 1 "general_operand" "rYs,m")))] + "msp430x" + "@ + MOV.B\t%1, %0 + MOV%X1.B\t%1, %0" +) + (define_insn "zero_extendqisi2" - [(set (match_operand:SI 0 "msp430_general_dst_nonv_operand" "=r") - (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "rm")))] + [(set (match_operand:SI 0 "msp430_general_dst_nonv_operand" "=r,r") + (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0,rm")))] "" - "MOV%X1.B\t%1,%L0 { CLR\t%H0" + "@ + CLR\t%H0 + MOV%X1.B\t%1,%L0 { CLR\t%H0" ) (define_insn "zero_extendhipsi2" - [(set (match_operand:PSI 0 "msp430_general_dst_operand" "=r,m") - (zero_extend:PSI (match_operand:HI 1 "msp430_general_operand" "rm,r")))] - "" + [(set (match_operand:PSI 0 "msp430_general_dst_operand" "=r,r,m") + (zero_extend:PSI (match_operand:HI 1 "msp430_general_operand" "rYs,m,r")))] + "msp430x" "@ - MOVX\t%1, %0 + MOV.W\t%1, %0 + MOV%X1\t%1, %0 MOVX.A\t%1, %0" ) @@ -616,22 +647,90 @@ ; the pair is unused and so it can clobber it. Try compiling 20050826-2.c ; at -O2 to see this. +; FIXME we can use MOVA for r->m if m is &abs20 or z16(rdst) (define_insn "zero_extendpsisi2" - [(set (match_operand:SI 0 "register_operand" "+r") - (zero_extend:SI (match_operand:PSI 1 "register_operand" "r")))] + [(set (match_operand:SI 0 "register_operand" "+r,m") + (zero_extend:SI (match_operand:PSI 1 "register_operand" "r,r")))] "" - "* - if (REGNO (operands[1]) == SP_REGNO) - /* If the source register is the stack pointer, the value - stored in the stack slot will be the value *after* the - stack pointer has been decremented. So allow for that - here. */ - return \"PUSHM.A\t#1, %1 { ADDX.W\t#4, @r1 { POPX.W\t%L0 { POPX.W\t%H0 ; get stack pointer into %L0:%H0\"; - else + "@ + * if (REGNO (operands[1]) == SP_REGNO) \ + /* If the source register is the stack pointer, the value \ + stored in the stack slot will be the value *after* the \ + stack pointer has been decremented. So allow for that \ + here. */ \ + return \"PUSHM.A\t#1, %1 { ADDX.W\t#4, @r1 { POPX.W\t%L0 { POPX.W\t%H0 ; get stack pointer into %L0:%H0\"; \ + else \ return \"PUSHM.A\t#1, %1 { POPX.W\t%L0 { POPX.W\t%H0 ; move pointer in %1 into reg-pair %L0:%H0\"; - " + MOVX.A %1, %0" +) + +;; Below are unnamed insn patterns to catch pointer manipulation insns +;; generated by combine. +;; We get large code size bloat when a PSImode pointer is stored in +;; memory, so we try to avoid that where possible and keep point manipulation +;; between registers. +; FIXME many of these should be unnnecessary once combine deals with +; (sign_extend (zero_extend)) or (sign_extend (subreg)) BZ 91865. + +;; This is just another way of writing movqipsi/zero_extendqipsi +(define_insn "" + [(set (match_operand:PSI 0 "register_operand" "=r") + (sign_extend:PSI (subreg:HI (match_operand:QI 1 "general_operand" "rm") 0)))] + "msp430x" + "MOV%X1.B\t%1, %0" +) + +(define_insn "" + [(set (match_operand:PSI 0 "register_operand" "=r,r") + (sign_extend:PSI (zero_extend:HI (match_operand:QI 1 "general_operand" "rYs,m"))))] + "msp430x" + "@ + MOV.B\t%1, %0 + MOV%X1.B\t%1, %0" +) + +(define_insn "" + [(set (match_operand:SI 0 "register_operand" "=r") + (ashift:SI (zero_extend:SI (match_operand:QI 1 "general_operand" "rm")) + (match_operand:HI 2 "immediate_operand" "M")))] + "msp430x" + "MOV%X1.B %1, %L0 { RLAM.W %2, %L0 { CLR %H0" ) +;; We are taking a char and shifting it and putting the result in 2 registers. +;; the high register will always be for 0 shift counts < 8. +(define_insn "" + [(set (match_operand:SI 0 "register_operand" "=r") + (ashift:SI (zero_extend:SI (subreg:HI (match_operand:QI 1 "general_operand" "rm") 0)) + (match_operand:HI 2 "immediate_operand" "M")))] + "msp430x" + "MOV%X1.B %1, %L0 { RLAM.W %2, %L0 { CLR %H0" +) + +;; Same as above but with a NOP sign_extend round the subreg +(define_insn "" + [(set (match_operand:SI 0 "register_operand" "=r") + (ashift:SI (zero_extend:SI (sign_extend:PSI (subreg:HI (match_operand:QI 1 "general_operand" "rm") 0))) + (match_operand:HI 2 "immediate_operand" "M")))] + "msp430x" + "MOV%X1.B %1, %L0 { RLAM.W %2, %L0 { CLR %H0" +) + +(define_insn "" + [(set (match_operand:SI 0 "register_operand" "=r") + (zero_extend:SI (sign_extend:PSI (subreg:HI (match_operand:QI 1 "general_operand" "rm") 0))))] + "msp430x" + "MOV%X1.B %1, %L0 { CLR %H0" +) + +(define_insn "" + [(set (match_operand:PSI 0 "register_operand" "=r") + (ashift:PSI (sign_extend:PSI (subreg:HI (match_operand:QI 1 "general_operand" "rm") 0)) + (match_operand:HI 2 "immediate_operand" "M")))] + "msp430x" + "MOV%X1.B %1, %0 { RLAM.W %2, %0" +) +;; END msp430 pointer manipulation combine insn patterns ;; Eliminate extraneous zero-extends mysteriously created by gcc. (define_peephole2 -- 2.17.1