From patchwork Tue Jul 2 08:51:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ilya Leoshkevich X-Patchwork-Id: 1126073 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-504144-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="pJ3CkPP7"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 45dHzy1Rbbz9s00 for ; Tue, 2 Jul 2019 18:52:14 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:mime-version:content-transfer-encoding :message-id; q=dns; s=default; b=ppIYNoorvWohjRSc6vBRQzGkJCqR+d9 3Tb+WBot09mpjkzN0mmOQYCguqcwkxIeU8hNDPrXjmfPBEvQKujVg16Utnqvn1z1 ft4uBt9pzxzxD+RWtcMQ6W2B47S6kiJGkP0tZa7E3Hlu82UL4Ajl/YWgxbpt3oZ1 3zh3tlBH/+So= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:mime-version:content-transfer-encoding :message-id; s=default; bh=KlWnj84aBaB6f/d2b8eUZ+t4Eeo=; b=pJ3Ck PP7IjSH3Vy8mP02Ms2qOBUuQzDQJlry7N1ERH4D5chNyB8SbobiDly9wCTNDWmeU H7o3bqx+ipONvPGcaKNHktUo5E7ngiLrqvbrNl87OQ5c7WSCzHJFDQRMPxva6wHh oYq7vTHr/Xou8VRdi+18omLLZIh9sZdigypdPA= Received: (qmail 105562 invoked by alias); 2 Jul 2019 08:52:07 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 105543 invoked by uid 89); 2 Jul 2019 08:52:06 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-15.1 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.1 spammy= X-HELO: mx0a-001b2d01.pphosted.com Received: from mx0b-001b2d01.pphosted.com (HELO mx0a-001b2d01.pphosted.com) (148.163.158.5) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 02 Jul 2019 08:52:04 +0000 Received: from pps.filterd (m0098413.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x628lPnd033348 for ; Tue, 2 Jul 2019 04:52:02 -0400 Received: from e06smtp01.uk.ibm.com (e06smtp01.uk.ibm.com [195.75.94.97]) by mx0b-001b2d01.pphosted.com with ESMTP id 2tg3j0hev3-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Tue, 02 Jul 2019 04:52:01 -0400 Received: from localhost by e06smtp01.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Tue, 2 Jul 2019 09:51:59 +0100 Received: from d06av22.portsmouth.uk.ibm.com (d06av22.portsmouth.uk.ibm.com [9.149.105.58]) by b06cxnps4076.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x628pvT845809706 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 2 Jul 2019 08:51:57 GMT Received: from d06av22.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id D558C4C044; Tue, 2 Jul 2019 08:51:57 +0000 (GMT) Received: from d06av22.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id AA1814C059; Tue, 2 Jul 2019 08:51:57 +0000 (GMT) Received: from white.boeblingen.de.ibm.com (unknown [9.152.98.98]) by d06av22.portsmouth.uk.ibm.com (Postfix) with ESMTP; Tue, 2 Jul 2019 08:51:57 +0000 (GMT) From: Ilya Leoshkevich To: gcc-patches@gcc.gnu.org, krebbel@linux.ibm.com, jakub@redhat.com Cc: Ilya Leoshkevich Subject: [PATCH] S/390: Improve storing asan frame_pc Date: Tue, 2 Jul 2019 10:51:54 +0200 MIME-Version: 1.0 x-cbid: 19070208-4275-0000-0000-000003484D26 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19070208-4276-0000-0000-00003858635B Message-Id: <20190702085154.26981-1-iii@linux.ibm.com> X-IsSubscribed: yes Bootstrapped and regtested on x86_64-redhat-linux, s390x-redhat-linux and ppc64le-redhat-linux. Currently s390 emits the following sequence to store a frame_pc: a: .LASANPC0: lg %r1,.L5-.L4(%r13) la %r1,0(%r1,%r12) stg %r1,176(%r11) .L5: .quad .LASANPC0@GOTOFF The reason GOT indirection is used instead of larl is that gcc does not know that .LASANPC0, being a code label, is aligned on a 2-byte boundary, and larl can load only even addresses. This patch provides such an alignment hint. Since targets don't provide their instruction alignments yet, the new hook is introduced for that purpose. It returns 1-byte alignment by default, so this change is a no-op for targets other than s390. As a result, we get the desired: larl %r1,.LASANPC0 stg %r1,176(%r11) gcc/ChangeLog: 2019-06-28 Ilya Leoshkevich * asan.c (asan_emit_stack_protection): Provide an alignment hint. * config/s390/s390.c (TARGET_INSN_ALIGNMENT): Specify that s390 requires instructions to be aligned on a 2-byte boundary. * doc/tm.texi: Document TARGET_INSN_ALIGNMENT. * doc/tm.texi.in: Likewise. * target.def (insn_alignment): New hook. gcc/testsuite/ChangeLog: 2019-06-28 Ilya Leoshkevich * gcc.target/s390/asan-no-gotoff.c: New test. --- gcc/asan.c | 1 + gcc/config/s390/s390.c | 3 +++ gcc/doc/tm.texi | 7 +++++++ gcc/doc/tm.texi.in | 2 ++ gcc/target.def | 9 +++++++++ gcc/testsuite/gcc.target/s390/asan-no-gotoff.c | 15 +++++++++++++++ 6 files changed, 37 insertions(+) create mode 100644 gcc/testsuite/gcc.target/s390/asan-no-gotoff.c diff --git a/gcc/asan.c b/gcc/asan.c index 605d04f87f7..c436f437375 100644 --- a/gcc/asan.c +++ b/gcc/asan.c @@ -1523,6 +1523,7 @@ asan_emit_stack_protection (rtx base, rtx pbase, unsigned int alignb, DECL_INITIAL (decl) = decl; TREE_ASM_WRITTEN (decl) = 1; TREE_ASM_WRITTEN (id) = 1; + SET_DECL_ALIGN (decl, targetm.insn_alignment); emit_move_insn (mem, expand_normal (build_fold_addr_expr (decl))); shadow_base = expand_binop (Pmode, lshr_optab, base, gen_int_shift_amount (Pmode, ASAN_SHADOW_SHIFT), diff --git a/gcc/config/s390/s390.c b/gcc/config/s390/s390.c index 5ec26a0592b..7ac2c8bdf76 100644 --- a/gcc/config/s390/s390.c +++ b/gcc/config/s390/s390.c @@ -16651,6 +16651,9 @@ s390_sched_dependencies_evaluation (rtx_insn *head, rtx_insn *tail) #undef TARGET_MAX_ANCHOR_OFFSET #define TARGET_MAX_ANCHOR_OFFSET 0xfff +#undef TARGET_INSN_ALIGNMENT +#define TARGET_INSN_ALIGNMENT 16 + struct gcc_target targetm = TARGET_INITIALIZER; #include "gt-s390.h" diff --git a/gcc/doc/tm.texi b/gcc/doc/tm.texi index 14c1ea6a323..142c7c04c46 100644 --- a/gcc/doc/tm.texi +++ b/gcc/doc/tm.texi @@ -1464,6 +1464,13 @@ appropriate for a target that does not define any new fundamental types. @end deftypefn +@deftypevr {Target Hook} HOST_WIDE_INT TARGET_INSN_ALIGNMENT +Certain architectures require individual machine instructions to +be aligned - e.g. on a 4-byte boundary on arm, mips and ppc, or +on a 2-byte boundary on s390. Define this to specify such +instruction alignment in bits. The default value is 8. +@end deftypevr + @node Type Layout @section Layout of Source Language Data Types diff --git a/gcc/doc/tm.texi.in b/gcc/doc/tm.texi.in index b4d57b86e2f..97578d6de27 100644 --- a/gcc/doc/tm.texi.in +++ b/gcc/doc/tm.texi.in @@ -1282,6 +1282,8 @@ pattern needs to support both a 32- and a 64-bit mode. @hook TARGET_MANGLE_TYPE +@hook TARGET_INSN_ALIGNMENT + @node Type Layout @section Layout of Source Language Data Types diff --git a/gcc/target.def b/gcc/target.def index 41654054ad8..1f6fac4b830 100644 --- a/gcc/target.def +++ b/gcc/target.def @@ -3185,6 +3185,15 @@ DEFHOOK bool, (struct ao_ref *ref), default_ref_may_alias_errno) +/* Machine instruction alignment. */ +DEFHOOKPOD +(insn_alignment, + "Certain architectures require individual machine instructions to\n\ +be aligned - e.g. on a 4-byte boundary on arm, mips and ppc, or\n\ +on a 2-byte boundary on s390. Define this to specify such\n\ +instruction alignment in bits. The default value is 8.", + HOST_WIDE_INT, 8) + /* Support for named address spaces. */ #undef HOOK_PREFIX #define HOOK_PREFIX "TARGET_ADDR_SPACE_" diff --git a/gcc/testsuite/gcc.target/s390/asan-no-gotoff.c b/gcc/testsuite/gcc.target/s390/asan-no-gotoff.c new file mode 100644 index 00000000000..f555e4e96f8 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/asan-no-gotoff.c @@ -0,0 +1,15 @@ +/* Test that ASAN labels are referenced without unnecessary indirections. */ + +/* { dg-do compile } */ +/* { dg-options "-fPIE -O2 -fsanitize=kernel-address --param asan-stack=1" } */ + +extern void c (int *); + +void a () +{ + int b; + c (&b); +} + +/* { dg-final { scan-assembler {\tlarl\t%r\d+,\.LASANPC\d+} } } */ +/* { dg-final { scan-assembler-not {\.LASANPC\d+@GOTOFF} } } */