| Message ID | 20190515124006.25840-13-christophe.lyon@st.com |
|---|---|
| State | New |
| Headers | show |
| Series | FDPIC ABI for ARM | expand |
Here is an updated version that makes use of the helper gen_restore_pic_register_after_call Christophe On 15/05/2019 14:39, Christophe Lyon wrote: > We call __aeabi_read_tp() to get the thread pointer. Since this is a > function call, we have to restore the FDPIC register afterwards. > > 2019-XX-XX Christophe Lyon <christophe.lyon@st.com> > Mickaël Guêné <mickael.guene@st.com> > > gcc/ > * config/arm/arm.c (arm_load_tp): Add FDPIC support. > * config/arm/arm.md (load_tp_soft_fdpic): New pattern. > (load_tp_soft): Disable in FDPIC mode. > > Change-Id: I1f6dfaee6260ecb453270f4971b3c5124317a186 > > diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c > index 5fc7a20..26f29c7 100644 > --- a/gcc/config/arm/arm.c > +++ b/gcc/config/arm/arm.c > @@ -8732,7 +8732,25 @@ arm_load_tp (rtx target) > > rtx tmp; > > - emit_insn (gen_load_tp_soft ()); > + if (TARGET_FDPIC) > + { > + rtx par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (3)); > + rtx fdpic_reg = gen_rtx_REG (Pmode, FDPIC_REGNUM); > + rtx initial_fdpic_reg = get_hard_reg_initial_val (Pmode, FDPIC_REGNUM); > + > + emit_insn (gen_load_tp_soft_fdpic ()); > + > + /* Restore r9. */ > + XVECEXP (par, 0, 0) = gen_rtx_UNSPEC (VOIDmode, > + gen_rtvec (2, fdpic_reg, > + initial_fdpic_reg), > + UNSPEC_PIC_RESTORE); > + XVECEXP (par, 0, 1) = gen_rtx_USE (VOIDmode, initial_fdpic_reg); > + XVECEXP (par, 0, 2) = gen_rtx_CLOBBER (VOIDmode, fdpic_reg); > + emit_insn (par); > + } > + else > + emit_insn (gen_load_tp_soft ()); > > tmp = gen_rtx_REG (SImode, R0_REGNUM); > emit_move_insn (target, tmp); > diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md > index 9036255..0edcb1d 100644 > --- a/gcc/config/arm/arm.md > +++ b/gcc/config/arm/arm.md > @@ -11759,12 +11759,25 @@ > ) > > ;; Doesn't clobber R1-R3. Must use r0 for the first operand. > +(define_insn "load_tp_soft_fdpic" > + [(set (reg:SI 0) (unspec:SI [(const_int 0)] UNSPEC_TLS)) > + (clobber (reg:SI 9)) > + (clobber (reg:SI LR_REGNUM)) > + (clobber (reg:SI IP_REGNUM)) > + (clobber (reg:CC CC_REGNUM))] > + "TARGET_SOFT_TP && TARGET_FDPIC" > + "bl\\t__aeabi_read_tp\\t@ load_tp_soft" > + [(set_attr "conds" "clob") > + (set_attr "type" "branch")] > +) > + > +;; Doesn't clobber R1-R3. Must use r0 for the first operand. > (define_insn "load_tp_soft" > [(set (reg:SI 0) (unspec:SI [(const_int 0)] UNSPEC_TLS)) > (clobber (reg:SI LR_REGNUM)) > (clobber (reg:SI IP_REGNUM)) > (clobber (reg:CC CC_REGNUM))] > - "TARGET_SOFT_TP" > + "TARGET_SOFT_TP && !TARGET_FDPIC" > "bl\\t__aeabi_read_tp\\t@ load_tp_soft" > [(set_attr "conds" "clob") > (set_attr "type" "branch")]
Hi Christophe, On 5/15/19 1:39 PM, Christophe Lyon wrote: > We call __aeabi_read_tp() to get the thread pointer. Since this is a > function call, we have to restore the FDPIC register afterwards. > > 2019-XX-XX Christophe Lyon <christophe.lyon@st.com> > Mickaël Guêné <mickael.guene@st.com> > > gcc/ > * config/arm/arm.c (arm_load_tp): Add FDPIC support. > * config/arm/arm.md (load_tp_soft_fdpic): New pattern. > (load_tp_soft): Disable in FDPIC mode. > > Change-Id: I1f6dfaee6260ecb453270f4971b3c5124317a186 > > diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c > index 5fc7a20..26f29c7 100644 > --- a/gcc/config/arm/arm.c > +++ b/gcc/config/arm/arm.c > @@ -8732,7 +8732,25 @@ arm_load_tp (rtx target) > > rtx tmp; > > - emit_insn (gen_load_tp_soft ()); > + if (TARGET_FDPIC) > + { > + rtx par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (3)); > + rtx fdpic_reg = gen_rtx_REG (Pmode, FDPIC_REGNUM); > + rtx initial_fdpic_reg = get_hard_reg_initial_val (Pmode, > FDPIC_REGNUM); > + > + emit_insn (gen_load_tp_soft_fdpic ()); > + > + /* Restore r9. */ > + XVECEXP (par, 0, 0) = gen_rtx_UNSPEC (VOIDmode, > + gen_rtvec (2, fdpic_reg, > + initial_fdpic_reg), > + UNSPEC_PIC_RESTORE); > + XVECEXP (par, 0, 1) = gen_rtx_USE (VOIDmode, initial_fdpic_reg); > + XVECEXP (par, 0, 2) = gen_rtx_CLOBBER (VOIDmode, fdpic_reg); > + emit_insn (par); > + } > + else > + emit_insn (gen_load_tp_soft ()); > > tmp = gen_rtx_REG (SImode, R0_REGNUM); > emit_move_insn (target, tmp); > diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md > index 9036255..0edcb1d 100644 > --- a/gcc/config/arm/arm.md > +++ b/gcc/config/arm/arm.md > @@ -11759,12 +11759,25 @@ > ) > > ;; Doesn't clobber R1-R3. Must use r0 for the first operand. > +(define_insn "load_tp_soft_fdpic" > + [(set (reg:SI 0) (unspec:SI [(const_int 0)] UNSPEC_TLS)) > + (clobber (reg:SI 9)) Use FDPIC_REGNUM here (does it need to be declared at the top of arm.md for it to work?) Otherwise this is ok. Thanks, Kyrill > + (clobber (reg:SI LR_REGNUM)) > + (clobber (reg:SI IP_REGNUM)) > + (clobber (reg:CC CC_REGNUM))] > + "TARGET_SOFT_TP && TARGET_FDPIC" > + "bl\\t__aeabi_read_tp\\t@ load_tp_soft" > + [(set_attr "conds" "clob") > + (set_attr "type" "branch")] > +) > + > +;; Doesn't clobber R1-R3. Must use r0 for the first operand. > (define_insn "load_tp_soft" > [(set (reg:SI 0) (unspec:SI [(const_int 0)] UNSPEC_TLS)) > (clobber (reg:SI LR_REGNUM)) > (clobber (reg:SI IP_REGNUM)) > (clobber (reg:CC CC_REGNUM))] > - "TARGET_SOFT_TP" > + "TARGET_SOFT_TP && !TARGET_FDPIC" > "bl\\t__aeabi_read_tp\\t@ load_tp_soft" > [(set_attr "conds" "clob") > (set_attr "type" "branch")] > -- > 2.6.3 >
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 5fc7a20..26f29c7 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -8732,7 +8732,25 @@ arm_load_tp (rtx target) rtx tmp; - emit_insn (gen_load_tp_soft ()); + if (TARGET_FDPIC) + { + rtx par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (3)); + rtx fdpic_reg = gen_rtx_REG (Pmode, FDPIC_REGNUM); + rtx initial_fdpic_reg = get_hard_reg_initial_val (Pmode, FDPIC_REGNUM); + + emit_insn (gen_load_tp_soft_fdpic ()); + + /* Restore r9. */ + XVECEXP (par, 0, 0) = gen_rtx_UNSPEC (VOIDmode, + gen_rtvec (2, fdpic_reg, + initial_fdpic_reg), + UNSPEC_PIC_RESTORE); + XVECEXP (par, 0, 1) = gen_rtx_USE (VOIDmode, initial_fdpic_reg); + XVECEXP (par, 0, 2) = gen_rtx_CLOBBER (VOIDmode, fdpic_reg); + emit_insn (par); + } + else + emit_insn (gen_load_tp_soft ()); tmp = gen_rtx_REG (SImode, R0_REGNUM); emit_move_insn (target, tmp); diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 9036255..0edcb1d 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -11759,12 +11759,25 @@ ) ;; Doesn't clobber R1-R3. Must use r0 for the first operand. +(define_insn "load_tp_soft_fdpic" + [(set (reg:SI 0) (unspec:SI [(const_int 0)] UNSPEC_TLS)) + (clobber (reg:SI 9)) + (clobber (reg:SI LR_REGNUM)) + (clobber (reg:SI IP_REGNUM)) + (clobber (reg:CC CC_REGNUM))] + "TARGET_SOFT_TP && TARGET_FDPIC" + "bl\\t__aeabi_read_tp\\t@ load_tp_soft" + [(set_attr "conds" "clob") + (set_attr "type" "branch")] +) + +;; Doesn't clobber R1-R3. Must use r0 for the first operand. (define_insn "load_tp_soft" [(set (reg:SI 0) (unspec:SI [(const_int 0)] UNSPEC_TLS)) (clobber (reg:SI LR_REGNUM)) (clobber (reg:SI IP_REGNUM)) (clobber (reg:CC CC_REGNUM))] - "TARGET_SOFT_TP" + "TARGET_SOFT_TP && !TARGET_FDPIC" "bl\\t__aeabi_read_tp\\t@ load_tp_soft" [(set_attr "conds" "clob") (set_attr "type" "branch")]