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[73.93.86.59]) by smtp.gmail.com with ESMTPSA id s1sm10272808pgv.30.2019.02.18.10.37.00 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Feb 2019 10:37:02 -0800 (PST) Received: from gnu-cfl-2.hsd1.ca.comcast.net (localhost [IPv6:::1]) by gnu-cfl-2.localdomain (Postfix) with ESMTP id A897FC0330; Mon, 18 Feb 2019 10:36:57 -0800 (PST) From: "H.J. Lu" To: gcc-patches@gcc.gnu.org Cc: Uros Bizjak Subject: [PATCH 06/41] i386: Emulate MMX smulv4hi3_highpart with SSE Date: Mon, 18 Feb 2019 10:36:22 -0800 Message-Id: <20190218183657.16296-7-hjl.tools@gmail.com> In-Reply-To: <20190218183657.16296-1-hjl.tools@gmail.com> References: <20190218183657.16296-1-hjl.tools@gmail.com> MIME-Version: 1.0 X-IsSubscribed: yes Emulate MMX mulv4hi3 with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_smulv4hi3_highpart): Also allow TARGET_MMX_WITH_SSE. (*mmx_smulv4hi3_highpart): Also allow TARGET_MMX_WITH_SSE. Add SSE support. --- gcc/config/i386/mmx.md | 25 +++++++++++++++---------- 1 file changed, 15 insertions(+), 10 deletions(-) diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index fd0189eae60..01c80602b5b 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -748,27 +748,32 @@ (lshiftrt:V4SI (mult:V4SI (sign_extend:V4SI - (match_operand:V4HI 1 "nonimmediate_operand")) + (match_operand:V4HI 1 "register_mmxmem_operand")) (sign_extend:V4SI - (match_operand:V4HI 2 "nonimmediate_operand"))) + (match_operand:V4HI 2 "register_mmxmem_operand"))) (const_int 16))))] - "TARGET_MMX" + "TARGET_MMX || TARGET_MMX_WITH_SSE" "ix86_fixup_binary_operands_no_copy (MULT, V4HImode, operands);") (define_insn "*mmx_smulv4hi3_highpart" - [(set (match_operand:V4HI 0 "register_operand" "=y") + [(set (match_operand:V4HI 0 "register_operand" "=y,x,Yv") (truncate:V4HI (lshiftrt:V4SI (mult:V4SI (sign_extend:V4SI - (match_operand:V4HI 1 "nonimmediate_operand" "%0")) + (match_operand:V4HI 1 "register_mmxmem_operand" "%0,0,Yv")) (sign_extend:V4SI - (match_operand:V4HI 2 "nonimmediate_operand" "ym"))) + (match_operand:V4HI 2 "register_mmxmem_operand" "ym,x,Yv"))) (const_int 16))))] - "TARGET_MMX && ix86_binary_operator_ok (MULT, V4HImode, operands)" - "pmulhw\t{%2, %0|%0, %2}" - [(set_attr "type" "mmxmul") - (set_attr "mode" "DI")]) + "(TARGET_MMX || TARGET_MMX_WITH_SSE) + && ix86_binary_operator_ok (MULT, V4HImode, operands)" + "@ + pmulhw\t{%2, %0|%0, %2} + pmulhw\t{%2, %0|%0, %2} + vpmulhw\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "mmx_isa" "native,x64_noavx,x64_avx") + (set_attr "type" "mmxmul,ssemul,ssemul") + (set_attr "mode" "DI,TI,TI")]) (define_expand "mmx_umulv4hi3_highpart" [(set (match_operand:V4HI 0 "register_operand")