[35/41] i386: Emulate MMX abs<mode>2 with SSE

Message ID	20190218183657.16296-36-hjl.tools@gmail.com
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Headers	show Return-Path: <gcc-patches-return-496551-incoming=patchwork.ozlabs.org@gcc.gnu.org> DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; q=dns; s=default; b=ImV nviIaKoZLmGZ16gDMravF/x2MYR86/8nmOixxVP34PiWgO50ihANx7yBY0LPDyFT FKI6TFri4GyI3ARczScz7E4KZwnlGIWCZh7FNxcOPxayNYPC2kxcia5J1cfdSL3+ d3ZVee621jU3QwZVRHj9edUtX8Wy05CsKbd9lfxY= Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk Sender: gcc-patches-owner@gcc.gnu.org From: "H.J. Lu" <hjl.tools@gmail.com> To: gcc-patches@gcc.gnu.org Cc: Uros Bizjak <ubizjak@gmail.com> Subject: [PATCH 35/41] i386: Emulate MMX abs<mode>2 with SSE Date: Mon, 18 Feb 2019 10:36:51 -0800 Message-Id: <20190218183657.16296-36-hjl.tools@gmail.com> In-Reply-To: <20190218183657.16296-1-hjl.tools@gmail.com> References: <20190218183657.16296-1-hjl.tools@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit
Series	V9: Emulate MMX intrinsics with SSE \| expand [00/41] V9: Emulate MMX intrinsics with SSE [01/41] i386: Allow MMX register modes in SSE registers [02/41] i386: Emulate MMX packsswb/packssdw/packuswb with SSE2 [03/41] i386: Emulate MMX punpcklXX/punpckhXX with SSE punpcklXX [04/41] i386: Emulate MMX plusminus/sat_plusminus with SSE [05/41] i386: Emulate MMX mulv4hi3 with SSE [06/41] i386: Emulate MMX smulv4hi3_highpart with SSE [07/41] i386: Emulate MMX mmx_pmaddwd with SSE [08/41] i386: Emulate MMX ashr<mode>3/<shift_insn><mode>3 with SSE [09/41] i386: Emulate MMX <any_logic><mode>3 with SSE [10/41] i386: Emulate MMX mmx_andnot<mode>3 with SSE [11/41] i386: Emulate MMX mmx_eq/mmx_gt<mode>3 with SSE [12/41] i386: Emulate MMX vec_dupv2si with SSE [13/41] i386: Emulate MMX pshufw with SSE [14/41] i386: Emulate MMX sse_cvtps2pi/sse_cvttps2pi with SSE [15/41] i386: Emulate MMX sse_cvtpi2ps with SSE [16/41] i386: Emulate MMX mmx_pextrw with SSE [17/41] i386: Emulate MMX mmx_pinsrw with SSE [18/41] i386: Emulate MMX V4HI smaxmin/V8QI umaxmin with SSE [19/41] i386: Emulate MMX mmx_pmovmskb with SSE [20/41] i386: Emulate MMX mmx_umulv4hi3_highpart with SSE [21/41] i386: Emulate MMX maskmovq with SSE2 maskmovdqu [22/41] i386: Emulate MMX mmx_uavgv8qi3 with SSE [23/41] i386: Emulate MMX mmx_uavgv4hi3 with SSE [24/41] i386: Emulate MMX mmx_psadbw with SSE [25/41] i386: Emulate MMX movntq with SSE2 movntidi [26/41] i386: Emulate MMX umulv1siv1di3 with SSE2 [27/41] i386: Make _mm_empty () as NOP without MMX [28/41] i386: Emulate MMX ssse3_ph<plusminus_mnemonic>wv4hi3 with SSE [29/41] i386: Emulate MMX ssse3_ph<plusminus_mnemonic>dv2si3 with SSE [30/41] i386: Emulate MMX ssse3_pmaddubsw with SSE [31/41] i386: Emulate MMX ssse3_pmulhrswv4hi3 with SSE [32/41] i386: Emulate MMX pshufb with SSE version [33/41] i386: Emulate MMX ssse3_psign<mode>3 with SSE [34/41] i386: Emulate MMX ssse3_palignrdi with SSE [35/41] i386: Emulate MMX abs<mode>2 with SSE [36/41] Prevent allocation of MMX registers with TARGET_MMX_WITH_SSE [37/41] i386: Allow MMXMODE moves with TARGET_MMX_WITH_SSE [38/41] i386: Allow MMX vector expanders with TARGET_MMX_WITH_SSE [39/41] i386: Allow MMX intrinsic emulation with SSE [40/41] i386: Enable TM MMX intrinsics with SSE2 [41/41] i386: Add tests for MMX intrinsic emulations with SSE

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20190218183657.16296-36-hjl.tools@gmail.com

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Subject: [PATCH 35/41] i386: Emulate MMX abs<mode>2 with SSE
Date: Mon, 18 Feb 2019 10:36:51 -0800
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Series

V9: Emulate MMX intrinsics with SSE | expand

Commit Message

H.J. Lu Feb. 18, 2019, 6:36 p.m. UTC

Emulate MMX abs<mode>2 with SSE.  Only SSE register source operand is
allowed.

	PR target/89021
	* config/i386/sse.md (abs<mode>2): Add SSE emulation.
---
 gcc/config/i386/sse.md | 15 +++++++++------
 1 file changed, 9 insertions(+), 6 deletions(-)

diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index b69a467291c..97ec3795b82 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -15973,16 +15973,19 @@ 
 })
 
 (define_insn "abs<mode>2"
-  [(set (match_operand:MMXMODEI 0 "register_operand" "=y")
+  [(set (match_operand:MMXMODEI 0 "register_operand" "=y,Yv")
 	(abs:MMXMODEI
-	  (match_operand:MMXMODEI 1 "nonimmediate_operand" "ym")))]
-  "TARGET_SSSE3"
-  "pabs<mmxvecsize>\t{%1, %0|%0, %1}";
-  [(set_attr "type" "sselog1")
+	  (match_operand:MMXMODEI 1 "register_mmxmem_operand" "ym,Yv")))]
+  "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSSE3"
+  "@
+   pabs<mmxvecsize>\t{%1, %0|%0, %1}
+   %vpabs<mmxvecsize>\t{%1, %0|%0, %1}"
+  [(set_attr "mmx_isa" "native,x64")
+   (set_attr "type" "sselog1")
    (set_attr "prefix_rep" "0")
    (set_attr "prefix_extra" "1")
    (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
-   (set_attr "mode" "DI")])
+   (set_attr "mode" "DI,TI")])
 
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 ;;

[35/41] i386: Emulate MMX abs<mode>2 with SSE

Commit Message

Patch