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[73.93.86.59]) by smtp.gmail.com with ESMTPSA id q28sm24723972pgl.35.2019.02.16.14.40.35 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 16 Feb 2019 14:40:37 -0800 (PST) Received: from gnu-cfl-2.hsd1.ca.comcast.net (localhost [IPv6:::1]) by gnu-cfl-2.localdomain (Postfix) with ESMTP id 0AABEC0330; Sat, 16 Feb 2019 14:40:33 -0800 (PST) From: "H.J. Lu" To: gcc-patches@gcc.gnu.org Cc: Uros Bizjak Subject: [PATCH 07/41] i386: Emulate MMX mmx_pmaddwd with SSE Date: Sat, 16 Feb 2019 14:39:58 -0800 Message-Id: <20190216224032.4889-8-hjl.tools@gmail.com> In-Reply-To: <20190216224032.4889-1-hjl.tools@gmail.com> References: <20190216224032.4889-1-hjl.tools@gmail.com> MIME-Version: 1.0 X-IsSubscribed: yes Emulate MMX pmaddwd with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_pmaddwd): Also allow TARGET_MMX_WITH_SSE. (*mmx_pmaddwd): Also allow TARGET_MMX_WITH_SSE. Add SSE support. --- gcc/config/i386/mmx.md | 25 +++++++++++++++---------- 1 file changed, 15 insertions(+), 10 deletions(-) diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index 01c80602b5b..fe746a487d1 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -810,11 +810,11 @@ (mult:V2SI (sign_extend:V2SI (vec_select:V2HI - (match_operand:V4HI 1 "nonimmediate_operand") + (match_operand:V4HI 1 "register_mmxmem_operand") (parallel [(const_int 0) (const_int 2)]))) (sign_extend:V2SI (vec_select:V2HI - (match_operand:V4HI 2 "nonimmediate_operand") + (match_operand:V4HI 2 "register_mmxmem_operand") (parallel [(const_int 0) (const_int 2)])))) (mult:V2SI (sign_extend:V2SI @@ -823,20 +823,20 @@ (sign_extend:V2SI (vec_select:V2HI (match_dup 2) (parallel [(const_int 1) (const_int 3)]))))))] - "TARGET_MMX" + "TARGET_MMX || TARGET_MMX_WITH_SSE" "ix86_fixup_binary_operands_no_copy (MULT, V4HImode, operands);") (define_insn "*mmx_pmaddwd" - [(set (match_operand:V2SI 0 "register_operand" "=y") + [(set (match_operand:V2SI 0 "register_operand" "=y,x,Yv") (plus:V2SI (mult:V2SI (sign_extend:V2SI (vec_select:V2HI - (match_operand:V4HI 1 "nonimmediate_operand" "%0") + (match_operand:V4HI 1 "register_mmxmem_operand" "%0,0,Yv") (parallel [(const_int 0) (const_int 2)]))) (sign_extend:V2SI (vec_select:V2HI - (match_operand:V4HI 2 "nonimmediate_operand" "ym") + (match_operand:V4HI 2 "register_mmxmem_operand" "ym,x,Yv") (parallel [(const_int 0) (const_int 2)])))) (mult:V2SI (sign_extend:V2SI @@ -845,10 +845,15 @@ (sign_extend:V2SI (vec_select:V2HI (match_dup 2) (parallel [(const_int 1) (const_int 3)]))))))] - "TARGET_MMX && ix86_binary_operator_ok (MULT, V4HImode, operands)" - "pmaddwd\t{%2, %0|%0, %2}" - [(set_attr "type" "mmxmul") - (set_attr "mode" "DI")]) + "(TARGET_MMX || TARGET_MMX_WITH_SSE) + && ix86_binary_operator_ok (MULT, V4HImode, operands)" + "@ + pmaddwd\t{%2, %0|%0, %2} + pmaddwd\t{%2, %0|%0, %2} + vpmaddwd\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "mmx_isa" "native,x64_noavx,x64_avx") + (set_attr "type" "mmxmul,sseiadd,sseiadd") + (set_attr "mode" "DI,TI,TI")]) (define_expand "mmx_pmulhrwv4hi3" [(set (match_operand:V4HI 0 "register_operand")