[26/43] i386: Emulate MMX umulv1siv1di3 with SSE2

Message ID	20190209132352.1828-27-hjl.tools@gmail.com
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Headers	show Return-Path: <gcc-patches-return-495591-incoming=patchwork.ozlabs.org@gcc.gnu.org> DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; q=dns; s=default; b=khL AvEd+ZDYIov9Cmpa3tEr5UVWFepOBp+cpkFKPKFQPAYcIP5c6vhunsPGTk6HSa1V 5K/SQpEtnE9pzqzzE0cOU2mp/xfYJoG+k58+zV3LGH6TrI+4W26x5f+r1VJLgIVM d0+Li+mP0mpoS0FQwsESyupDgJNIFjDbQfc9lNfI= Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk Sender: gcc-patches-owner@gcc.gnu.org From: "H.J. Lu" <hjl.tools@gmail.com> To: gcc-patches@gcc.gnu.org Cc: Uros Bizjak <ubizjak@gmail.com> Subject: [PATCH 26/43] i386: Emulate MMX umulv1siv1di3 with SSE2 Date: Sat, 9 Feb 2019 05:23:35 -0800 Message-Id: <20190209132352.1828-27-hjl.tools@gmail.com> In-Reply-To: <20190209132352.1828-1-hjl.tools@gmail.com> References: <20190209132352.1828-1-hjl.tools@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit
Series	V2: Emulate MMX intrinsics with SSE \| expand [00/43] V2: Emulate MMX intrinsics with SSE [01/43] i386: Allow 64-bit vector modes in SSE registers [02/43] i386: Emulate MMX packsswb/packssdw/packuswb with SSE2 [03/43] i386: Emulate MMX punpcklXX/punpckhXX with SSE punpcklXX [04/43] i386: Emulate MMX plusminus/sat_plusminus with SSE [05/43] i386: Emulate MMX mulv4hi3 with SSE [06/43] i386: Emulate MMX smulv4hi3_highpart with SSE [07/43] i386: Emulate MMX mmx_pmaddwd with SSE [08/43] i386: Emulate MMX ashr<mode>3/<shift_insn><mode>3 with SSE [09/43] i386: Emulate MMX <any_logic><mode>3 with SSE [10/43] i386: Emulate MMX mmx_andnot<mode>3 with SSE [11/43] i386: Emulate MMX mmx_eq/mmx_gt<mode>3 with SSE [12/43] i386: Emulate MMX vec_dupv2si with SSE [13/43] i386: Emulate MMX pshufw with SSE [14/43] i386: Emulate MMX sse_cvtps2pi/sse_cvttps2pi with SSE [15/43] i386: Emulate MMX sse_cvtpi2ps with SSE [16/43] i386: Emulate MMX mmx_pextrw with SSE [17/43] i386: Emulate MMX mmx_pinsrw with SSE [18/43] i386: Emulate MMX V4HI smaxmin/V8QI umaxmin with SSE [19/43] i386: Emulate MMX mmx_pmovmskb with SSE [20/43] i386: Emulate MMX mmx_umulv4hi3_highpart with SSE [21/43] i386: Emulate MMX maskmovq with SSE2 maskmovdqu [22/43] i386: Emulate MMX mmx_uavgv8qi3 with SSE [23/43] i386: Emulate MMX mmx_uavgv4hi3 with SSE [24/43] i386: Emulate MMX mmx_psadbw with SSE [25/43] i386: Emulate MMX movntq with SSE2 movntidi [26/43] i386: Emulate MMX umulv1siv1di3 with SSE2 [27/43] i386: Emulate MMX ssse3_ph<plusminus_mnemonic>wv4hi3 with SSE [28/43] i386: Emulate MMX ssse3_ph<plusminus_mnemonic>dv2si3 with SSE [29/43] i386: Emulate MMX ssse3_pmaddubsw with SSE [30/43] i386: Emulate MMX ssse3_pmulhrswv4hi3 with SSE [31/43] i386: Emulate MMX pshufb with SSE version [32/43] i386: Emulate MMX ssse3_psign<mode>3 with SSE [33/43] i386: Emulate MMX ssse3_palignrdi with SSE [34/43] i386: Emulate MMX abs<mode>2 with SSE [35/43] i386: Allow MMXMODE moves with TARGET_MMX_WITH_SSE [36/43] i386: Allow MMX vector expanders with TARGET_MMX_WITH_SSE [37/43] i386: Allow MMX intrinsic emulation with SSE [38/43] i386: Add tests for MMX intrinsic emulations with SSE [39/43] i386: Also enable SSSE3 __m64 tests in 64-bit mode [40/43] i386: Enable 8-byte vectorizer for TARGET_MMX_WITH_SSE [41/43] i386: Implement V2SF add/sub/mul with SEE [42/43] i386: Implement V2SF <-> V2SI conversions with SEE [43/43] i386: Implement V2SF comparisons with SSE

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Subject: [PATCH 26/43] i386: Emulate MMX umulv1siv1di3 with SSE2
Date: Sat,  9 Feb 2019 05:23:35 -0800
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Series

V2: Emulate MMX intrinsics with SSE | expand

Commit Message

H.J. Lu Feb. 9, 2019, 1:23 p.m. UTC

Emulate MMX umulv1siv1di3 with SSE2.  Only SSE register source operand
is allowed.

	PR target/89021
	* config/i386/mmx.md (*sse2_umulv1siv1di3): Add SSE2 emulation.
---
 gcc/config/i386/mmx.md | 16 ++++++++++------
 1 file changed, 10 insertions(+), 6 deletions(-)

diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md
index c52e5b2e393..f5e96ebe3f3 100644
--- a/gcc/config/i386/mmx.md
+++ b/gcc/config/i386/mmx.md
@@ -955,20 +955,24 @@ 
   "ix86_fixup_binary_operands_no_copy (MULT, V2SImode, operands);")
 
 (define_insn "*sse2_umulv1siv1di3"
-  [(set (match_operand:V1DI 0 "register_operand" "=y")
+  [(set (match_operand:V1DI 0 "register_operand" "=y,Yx,Yy")
         (mult:V1DI
 	  (zero_extend:V1DI
 	    (vec_select:V1SI
-	      (match_operand:V2SI 1 "nonimmediate_operand" "%0")
+	      (match_operand:V2SI 1 "nonimmediate_operand" "%0,0,Yy")
 	      (parallel [(const_int 0)])))
 	  (zero_extend:V1DI
 	    (vec_select:V1SI
-	      (match_operand:V2SI 2 "nonimmediate_operand" "ym")
+	      (match_operand:V2SI 2 "nonimmediate_operand" "ym,Yx,Yy")
 	      (parallel [(const_int 0)])))))]
   "TARGET_SSE2 && ix86_binary_operator_ok (MULT, V2SImode, operands)"
-  "pmuludq\t{%2, %0|%0, %2}"
-  [(set_attr "type" "mmxmul")
-   (set_attr "mode" "DI")])
+  "@
+   pmuludq\t{%2, %0|%0, %2}
+   pmuludq\t{%2, %0|%0, %2}
+   vpmuludq\t{%2, %1, %0|%0, %1, %2}"
+  [(set_attr "mmx_isa" "native,x64_noavx,x64_avx")
+   (set_attr "type" "mmxmul,ssemul,ssemul")
+   (set_attr "mode" "DI,TI,TI")])
 
 (define_expand "mmx_<code>v4hi3"
   [(set (match_operand:V4HI 0 "register_operand")

[26/43] i386: Emulate MMX umulv1siv1di3 with SSE2

Commit Message

Patch