From patchwork Sat Feb 9 13:23:27 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "H.J. Lu" X-Patchwork-Id: 1039208 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-495586-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="aIyc+gmM"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 43xXvb6yr2z9sMl for ; Sun, 10 Feb 2019 00:29:15 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; q=dns; s=default; b=HbW e9idRt1sSA6KqiaTYGNVJIq+7ElTw1qI9EZOkTo0djx8hwmnW9GorLwS8HbLfhfM JfKtJagDJoY+czKq+U0aMJiY+1gfHHnKePCRoSM2zTlqkuBUFe5+OTeIVp5UT4Ql bsXlbYswqPU8P9BBE+GH54LrMKLJ331jHFJGsaIk= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=default; bh=fSBHBJvk+ hZ/+fS5nGchG+wGY+0=; b=aIyc+gmMwth5Dw4gH97F8wdVgcOGKwnDCVWdfv3s1 Do+IlrH3FuNXy1M+ySGqGpJgDe6EoCCc3tTaqppFtSA1PPo3Xxaxs7pl9BKzMu/d D47wmmkQrdTLEd9aRwcHuJbMak5uD6BMCm9D/N1HaYWi2rRLYqPTyGJf94EUnkob Qs= Received: (qmail 92536 invoked by alias); 9 Feb 2019 13:25:39 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 90180 invoked by uid 89); 9 Feb 2019 13:24:05 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.2 required=5.0 tests=BAYES_00, FREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, SPF_SOFTFAIL autolearn=ham version=3.3.2 spammy=HContent-Transfer-Encoding:8bit X-HELO: mga01.intel.com Received: from mga01.intel.com (HELO mga01.intel.com) (192.55.52.88) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Sat, 09 Feb 2019 13:24:03 +0000 Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 09 Feb 2019 05:23:53 -0800 Received: from gnu-cfl-1.sc.intel.com ([172.25.70.237]) by fmsmga004.fm.intel.com with ESMTP; 09 Feb 2019 05:23:53 -0800 From: "H.J. Lu" To: gcc-patches@gcc.gnu.org Cc: Uros Bizjak Subject: [PATCH 18/43] i386: Emulate MMX V4HI smaxmin/V8QI umaxmin with SSE Date: Sat, 9 Feb 2019 05:23:27 -0800 Message-Id: <20190209132352.1828-19-hjl.tools@gmail.com> In-Reply-To: <20190209132352.1828-1-hjl.tools@gmail.com> References: <20190209132352.1828-1-hjl.tools@gmail.com> MIME-Version: 1.0 X-IsSubscribed: yes Emulate MMX V4HI smaxmin/V8QI umaxmin with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (smaxmin:v4hi3): New. (umaxmin:v8qi3): Likewise. (smaxmin:*mmx_v4hi3): Add SSE emulation. (umaxmin:*mmx_v8qi3): Likewise. --- gcc/config/i386/mmx.md | 48 +++++++++++++++++++++++++++++++----------- 1 file changed, 36 insertions(+), 12 deletions(-) diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index ad33e587352..ee5acb00a6d 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -960,16 +960,28 @@ "TARGET_SSE || TARGET_3DNOW_A" "ix86_fixup_binary_operands_no_copy (, V4HImode, operands);") +(define_expand "v4hi3" + [(set (match_operand:V4HI 0 "register_operand") + (smaxmin:V4HI + (match_operand:V4HI 1 "nonimmediate_operand") + (match_operand:V4HI 2 "nonimmediate_operand")))] + "TARGET_MMX_WITH_SSE" + "ix86_fixup_binary_operands_no_copy (, V4HImode, operands);") + (define_insn "*mmx_v4hi3" - [(set (match_operand:V4HI 0 "register_operand" "=y") + [(set (match_operand:V4HI 0 "register_operand" "=y,Yx,Yy") (smaxmin:V4HI - (match_operand:V4HI 1 "nonimmediate_operand" "%0") - (match_operand:V4HI 2 "nonimmediate_operand" "ym")))] + (match_operand:V4HI 1 "nonimmediate_operand" "%0,0,Yy") + (match_operand:V4HI 2 "nonimmediate_operand" "ym,Yx,Yy")))] "(TARGET_SSE || TARGET_3DNOW_A) && ix86_binary_operator_ok (, V4HImode, operands)" - "pw\t{%2, %0|%0, %2}" - [(set_attr "type" "mmxadd") - (set_attr "mode" "DI")]) + "@ + pw\t{%2, %0|%0, %2} + pw\t{%2, %0|%0, %2} + vpw\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "mmx_isa" "native,x64_noavx,x64_avx") + (set_attr "type" "mmxadd,sseiadd,sseiadd") + (set_attr "mode" "DI,TI,TI")]) (define_expand "mmx_v8qi3" [(set (match_operand:V8QI 0 "register_operand") @@ -979,16 +991,28 @@ "TARGET_SSE || TARGET_3DNOW_A" "ix86_fixup_binary_operands_no_copy (, V8QImode, operands);") +(define_expand "v8qi3" + [(set (match_operand:V8QI 0 "register_operand") + (umaxmin:V8QI + (match_operand:V8QI 1 "nonimmediate_operand") + (match_operand:V8QI 2 "nonimmediate_operand")))] + "TARGET_MMX_WITH_SSE" + "ix86_fixup_binary_operands_no_copy (, V8QImode, operands);") + (define_insn "*mmx_v8qi3" - [(set (match_operand:V8QI 0 "register_operand" "=y") + [(set (match_operand:V8QI 0 "register_operand" "=y,Yx,Yy") (umaxmin:V8QI - (match_operand:V8QI 1 "nonimmediate_operand" "%0") - (match_operand:V8QI 2 "nonimmediate_operand" "ym")))] + (match_operand:V8QI 1 "nonimmediate_operand" "%0,0,Yy") + (match_operand:V8QI 2 "nonimmediate_operand" "ym,Yx,Yy")))] "(TARGET_SSE || TARGET_3DNOW_A) && ix86_binary_operator_ok (, V8QImode, operands)" - "pb\t{%2, %0|%0, %2}" - [(set_attr "type" "mmxadd") - (set_attr "mode" "DI")]) + "@ + pb\t{%2, %0|%0, %2} + pb\t{%2, %0|%0, %2} + vpb\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "mmx_isa" "native,x64_noavx,x64_avx") + (set_attr "type" "mmxadd,sseiadd,sseiadd") + (set_attr "mode" "DI,TI,TI")]) (define_insn "mmx_ashr3" [(set (match_operand:MMXMODE24 0 "register_operand" "=y")