[35/46] i386: Emulate MMX ssse3_psign<mode>3 with SSE

Message ID	20190201211809.963-36-hjl.tools@gmail.com
State	New
Headers	show Return-Path: <gcc-patches-return-495140-incoming=patchwork.ozlabs.org@gcc.gnu.org> DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; q=dns; s=default; b=bmn ZHp9spn006GTPy/MJ2U1WEVNujrlFjICh40yiIrPwyTnM1DXXkEPF19g3FaYd8tc wZLX5s5Opo+U+ZKQ120NEfCh7gsXxIQOa5yPRHiLT99DHsaurWsb8uWaLD/rXonK RyJiyet0Et/Qo0s+Fz8CJDiLl/CtfHo6f1shU/GA= Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk Sender: gcc-patches-owner@gcc.gnu.org From: "H.J. Lu" <hjl.tools@gmail.com> To: gcc-patches@gcc.gnu.org Cc: Uros Bizjak <ubizjak@gmail.com> Subject: [PATCH 35/46] i386: Emulate MMX ssse3_psign<mode>3 with SSE Date: Fri, 1 Feb 2019 13:17:58 -0800 Message-Id: <20190201211809.963-36-hjl.tools@gmail.com> In-Reply-To: <20190201211809.963-1-hjl.tools@gmail.com> References: <20190201211809.963-1-hjl.tools@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit
Series	Implement MMX intrinsics with SSE \| expand [00/46] Implement MMX intrinsics with SSE [01/46] i386: Add TARGET_MMX_INSNS and TARGET_MMX_WITH_SSE [02/46] libitm: Support _ITM_TYPE_M64 with SSE2 in 64-bit mode [03/46] i386: Allow 64-bit vector modes in SSE registers [04/46] i386: Allow UNSPECV_EMMS with SSE2 in 64-bit mode [05/46] i386: Emulate MMX packsswb/packssdw/packuswb with SSE2 [06/46] i386: Emulate MMX punpcklXX/punpckhXX with SSE punpcklXX [07/46] i386: Emulate MMX plusminus/sat_plusminus with SSE [08/46] i386: Emulate MMX mulv4hi3 with SSE [09/46] i386: Emulate MMX smulv4hi3_highpart with SSE [10/46] i386: Emulate MMX mmx_pmaddwd with SSE [11/46] i386: Emulate MMX ashr<mode>3/<shift_insn><mode>3 with SSE [12/46] i386: Emulate MMX <any_logic><mode>3 with SSE [13/46] i386: Emulate MMX mmx_andnot<mode>3 with SSE [14/46] i386: Emulate MMX mmx_eq/mmx_gt<mode>3 with SSE [15/46] i386: Emulate MMX vec_dupv2si with SSE [16/46] i386: Emulate MMX pshufw with SSE [17/46] i386: Emulate MMX sse_cvtps2pi/sse_cvttps2pi with SSE [18/46] i386: Emulate MMX sse_cvtpi2ps with SSE [19/46] i386: Emulate MMX mmx_pextrw with SSE [20/46] i386: Emulate MMX mmx_pinsrw with SSE [21/46] i386: Emulate MMX V4HI smaxmin/V8QI umaxmin with SSE [22/46] i386: Emulate MMX mmx_pmovmskb with SSE [23/46] i386: Emulate MMX mmx_umulv4hi3_highpart with SSE [24/46] i386: Emulate MMX maskmovq with SSE2 maskmovdqu [25/46] i386: Emulate MMX mmx_uavgv8qi3 with SSE [26/46] i386: Emulate MMX mmx_uavgv4hi3 with SSE [27/46] i386: Emulate MMX mmx_psadbw with SSE [28/46] i386: Emulate MMX movntq with SSE2 movntidi [29/46] i386: Emulate MMX umulv1siv1di3 with SSE2 [30/46] i386: Emulate MMX ssse3_ph<plusminus_mnemonic>wv4hi3 with SSE [31/46] i386: Emulate MMX ssse3_ph<plusminus_mnemonic>dv2si3 with SSE [32/46] i386: Emulate MMX ssse3_pmaddubsw with SSE [33/46] i386: Emulate MMX ssse3_pmulhrswv4hi3 with SSE [34/46] i386: Emulate MMX pshufb with SSE version [35/46] i386: Emulate MMX ssse3_psign<mode>3 with SSE [36/46] i386: Emulate MMX ssse3_palignrdi with SSE [37/46] i386: Emulate MMX abs<mode>2 with SSE [38/46] i386: Allow MMXMODE moves without MMX [39/46] i386: Allow MMX vector expanders with SSE [40/46] i386: Don't enable MMX in 64-bit mode by default [41/46] i386: Add tests for MMX intrinsic emulations with SSE [42/46] i386: Also enable SSSE3 __m64 tests without MMX [43/46] i386: Enable 8-byte vectorizer for TARGET_MMX_WITH_SSE [44/46] i386: Implement V2SF add/sub/mul with SEE [45/46] i386: Implement V2SF <-> V2SI conversions with SEE [46/46] i386: Implement V2SF comparisons with SSE

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20190201211809.963-36-hjl.tools@gmail.com

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Subject: [PATCH 35/46] i386: Emulate MMX ssse3_psign<mode>3 with SSE
Date: Fri,  1 Feb 2019 13:17:58 -0800
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Series

Implement MMX intrinsics with SSE | expand

Commit Message

H.J. Lu Feb. 1, 2019, 9:17 p.m. UTC

Emulate MMX ssse3_psign<mode>3 with SSE.  Only SSE register source operand
is allowed.

	PR target/89021
	* config/i386/sse.md (ssse3_psign<mode>3): Add SSE emulation.
---
 gcc/config/i386/sse.md | 16 ++++++++++------
 1 file changed, 10 insertions(+), 6 deletions(-)

diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index f932369c740..6cad298eb86 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -15898,17 +15898,21 @@ 
    (set_attr "mode" "<sseinsnmode>")])
 
 (define_insn "ssse3_psign<mode>3"
-  [(set (match_operand:MMXMODEI 0 "register_operand" "=y")
+  [(set (match_operand:MMXMODEI 0 "register_operand" "=y,Yx,Yy")
 	(unspec:MMXMODEI
-	  [(match_operand:MMXMODEI 1 "register_operand" "0")
-	   (match_operand:MMXMODEI 2 "nonimmediate_operand" "ym")]
+	  [(match_operand:MMXMODEI 1 "register_operand" "0,0,Yy")
+	   (match_operand:MMXMODEI 2 "nonimmediate_operand" "ym,Yx,Yy")]
 	  UNSPEC_PSIGN))]
   "TARGET_SSSE3"
-  "psign<mmxvecsize>\t{%2, %0|%0, %2}";
-  [(set_attr "type" "sselog1")
+  "@
+   psign<mmxvecsize>\t{%2, %0|%0, %2}
+   psign<mmxvecsize>\t{%2, %0|%0, %2}
+   vpsign<mmxvecsize>\t{%2, %1, %0|%0, %1, %2}"
+  [(set_attr "isa" "*,noavx,avx")
+   (set_attr "type" "sselog1")
    (set_attr "prefix_extra" "1")
    (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
-   (set_attr "mode" "DI")])
+   (set_attr "mode" "DI,TI,TI")])
 
 (define_insn "<ssse3_avx2>_palignr<mode>_mask"
   [(set (match_operand:VI1_AVX512 0 "register_operand" "=v")

[35/46] i386: Emulate MMX ssse3_psign<mode>3 with SSE

Commit Message

Patch