Message ID | 20190123104257.GA20409@arm.com |
---|---|
State | New |
Headers | show |
Series | [wwwdocs,Arm,AArch64] Update changes with new features and flags. | expand |
Ping.
On Wed, Jan 23, 2019 at 04:43:02AM -0600, Tamar Christina wrote: > Hi All, > > This patch adds the documentation for Stack clash protection and Armv8.3-a support to > changes.html for GCC 9. > I have validated the html using the W3C validator. > > Ok for cvs? Almost OK by me. > > Thanks, > Tamar > > -- > Index: htdocs/gcc-9/changes.html > =================================================================== > RCS file: /cvs/gcc/wwwdocs/htdocs/gcc-9/changes.html,v > retrieving revision 1.35 > diff -u -r1.35 changes.html > --- htdocs/gcc-9/changes.html 15 Jan 2019 13:17:49 -0000 1.35 > +++ htdocs/gcc-9/changes.html 22 Jan 2019 11:16:07 -0000 > @@ -214,6 +214,27 @@ > <code>-mtune=cortex-a76.cortex-a55</code> or as arguments to the equivalent target > attributes and pragmas. > </li> > + <li> > + The AArch64 port now has support for stack clash protection using the > + <code>-fstack-clash-protection</code> option. The protection also works for > + SVE systems. The probing interval/guard size can be set by using I would drop this "also works" part. The option is just available for AArch64, SVE is a part of AArch64. Otherwise OK, though I don't remember if that is for me to OK, or someone else. Thanks, James > + <code>--param stack-clash-protection-guard-size=12|16</code>. > + The value of this parameter must be in bytes represented as a power of two. > + The only two supported values for this parameter are 12 and 16 being > + 4Kb (2^12) and 64Kb (2^16) respectively. > + > + The default value is 16 (64Kb) and can be changed at configure > + time using the flag <code>--with-stack-clash-protection-guard-size=12|16</code>. > + </li> > + <li> > + The Armv8.3-A complex number instructions are now supported via intrinsics > + when the option <code>-march=armv8.3-a</code> or equivalent is specified. > + For the half-precision floating-point variants of these instructions use the > + architecture extension flag <code>+fp16</code>, e.g. > + <code>-march=armv8.3-a+fp16</code>. > + > + The intrinsics are defined by the ACLE specification. > + </li> > </ul> > > <h3 id="arc">ARC</h3> > @@ -250,6 +271,15 @@ > (which have no known implementations) has been removed. > Note that Armv5T, Armv5TE and Armv5TEJ architectures remain supported. > </li> > + <li> > + The Armv8.3-A complex number instructions are now supported via intrinsics > + when the option <code>-march=armv8.3-a</code> or equivalent is specified. > + For the half-precision floating-point variants of these instructions use the > + architecture extension flag <code>+fp16</code>, e.g. > + <code>-march=armv8.3-a+fp16</code>. > + > + The intrinsics are defined by the ACLE specification. > + </li> > </ul> > > <!-- <h3 id="avr">AVR</h3> --> >
On 30/01/19 15:29, James Greenhalgh wrote: > On Wed, Jan 23, 2019 at 04:43:02AM -0600, Tamar Christina wrote: > > Hi All, > > > > This patch adds the documentation for Stack clash protection and Armv8.3-a support to > > changes.html for GCC 9. > > I have validated the html using the W3C validator. > > > > Ok for cvs? > > Almost OK by me. > > > > > Thanks, > > Tamar > > > > -- > > > Index: htdocs/gcc-9/changes.html > > =================================================================== > > RCS file: /cvs/gcc/wwwdocs/htdocs/gcc-9/changes.html,v > > retrieving revision 1.35 > > diff -u -r1.35 changes.html > > --- htdocs/gcc-9/changes.html 15 Jan 2019 13:17:49 -0000 1.35 > > +++ htdocs/gcc-9/changes.html 22 Jan 2019 11:16:07 -0000 > > @@ -214,6 +214,27 @@ > > <code>-mtune=cortex-a76.cortex-a55</code> or as arguments to the equivalent target > > attributes and pragmas. > > </li> > > + <li> > > + The AArch64 port now has support for stack clash protection using the > > + <code>-fstack-clash-protection</code> option. The protection also works for > > + SVE systems. The probing interval/guard size can be set by using > > I would drop this "also works" part. The option is just available for AArch64, > SVE is a part of AArch64. > > Otherwise OK, though I don't remember if that is for me to OK, or someone > else. > Maintainers can approve the relevant wwwdocs parts. The arm parts LGTM FWIW. Kyrill > Thanks, > James > > > + <code>--param stack-clash-protection-guard-size=12|16</code>. > > + The value of this parameter must be in bytes represented as a power of two. > > + The only two supported values for this parameter are 12 and 16 being > > + 4Kb (2^12) and 64Kb (2^16) respectively. > > + > > + The default value is 16 (64Kb) and can be changed at configure > > + time using the flag <code>--with-stack-clash-protection-guard-size=12|16</code>. > > + </li> > > + <li> > > + The Armv8.3-A complex number instructions are now supported via intrinsics > > + when the option <code>-march=armv8.3-a</code> or equivalent is specified. > > + For the half-precision floating-point variants of these instructions use the > > + architecture extension flag <code>+fp16</code>, e.g. > > + <code>-march=armv8.3-a+fp16</code>. > > + > > + The intrinsics are defined by the ACLE specification. > > + </li> > > </ul> > > > > <h3 id="arc">ARC</h3> > > @@ -250,6 +271,15 @@ > > (which have no known implementations) has been removed. > > Note that Armv5T, Armv5TE and Armv5TEJ architectures remain supported. > > </li> > > + <li> > > + The Armv8.3-A complex number instructions are now supported via intrinsics > > + when the option <code>-march=armv8.3-a</code> or equivalent is specified. > > + For the half-precision floating-point variants of these instructions use the > > + architecture extension flag <code>+fp16</code>, e.g. > > + <code>-march=armv8.3-a+fp16</code>. > > + > > + The intrinsics are defined by the ACLE specification. > > + </li> > > </ul> > > > > <!-- <h3 id="avr">AVR</h3> --> > > >
On Wed, 30 Jan 2019, James Greenhalgh wrote: > Otherwise OK, though I don't remember if that is for me to OK, or > someone else. Yes, it is. :-) (But I'll also have a look tonight if you want to wait for that Tamar, but that's only an offer. We can always iterate.) Gerald
Hi Gerald, Yup that's fine :) I won't be able to commit it before Monday anyway. Cheers, Tamar
On Wed, 23 Jan 2019, Tamar Christina wrote: > This patch adds the documentation for Stack clash protection and > Armv8.3-a support to changes.html for GCC 9. Some additional notes, all minor, for consideration before you commit. + The probing interval/guard size can be set by using + <code>--param stack-clash-protection-guard-size=12|16</code>. + The value of this parameter must be in bytes represented as a power of two. + The only two supported values for this parameter are 12 and 16 being + 4Kb (2^12) and 64Kb (2^16) respectively. This one keeps making me think every time I read it. What do you think of changing the second and third sentences to "The two supported values for this paramter are 12 (for a 4KiB size, 2^12) and 16 (for a 64KiB size, 2^16)." or something like that? Shorter and about the same contents? (Note, uppercase B or we'd refer to bits.) + The Armv8.3-A complex number instructions are now supported via intrinsics + when the option <code>-march=armv8.3-a</code> or equivalent is specified. + For the half-precision floating-point variants of these instructions use the + architecture extension flag <code>+fp16</code>, e.g. + <code>-march=armv8.3-a+fp16</code>. + + The intrinsics are defined by the ACLE specification. Note that these two visual paragraphs in HTML source will be merged into just one unless you add <p>...</p> around the two. Just pointing it out. + <li> + The Armv8.3-A complex number instructions are now supported via intrinsics + when the option <code>-march=armv8.3-a</code> or equivalent is specified. + For the half-precision floating-point variants of these instructions use the + architecture extension flag <code>+fp16</code>, e.g. + <code>-march=armv8.3-a+fp16</code>. + + The intrinsics are defined by the ACLE specification. + </li> I guess this duplication is hard to avoid between Arm and AArch64? Gerald
Hi Gerard, Thanks I'll make the suggested changes. About the duplication, we can avoid it if we have a "general" section for all Arm ports first and then subsections for Arm and AArch64 specific things. I'm not sure how the maintainers feel about such a re-organization though. Any opinions guys? Thanks, Tamar
On Thu, 31 Jan 2019, 10:09 Tamar Christina <Tamar.Christina@arm.com wrote: > Hi Gerard, > > Thanks I'll make the suggested changes. > > About the duplication, we can avoid it if we have a "general" section for > all Arm ports first and then subsections for Arm and AArch64 specific > things. > > I'm not sure how the maintainers feel about such a re-organization though. > Works for me R > > Any opinions guys? > > Thanks, > Tamar > > ________________________________________ > From: Gerald Pfeifer <gerald@pfeifer.com> > Sent: Thursday, January 31, 2019 12:29 AM > To: Tamar Christina > Cc: gcc-patches@gcc.gnu.org; nd; James Greenhalgh; Richard Earnshaw; > Marcus Shawcroft; Ramana Radhakrishnan; nickc@redhat.com; Kyrylo Tkachov > Subject: Re: [PATCH][wwwdocs][Arm][AArch64] Update changes with new > features and flags. > > On Wed, 23 Jan 2019, Tamar Christina wrote: > > This patch adds the documentation for Stack clash protection and > > Armv8.3-a support to changes.html for GCC 9. > > Some additional notes, all minor, for consideration before you commit. > > + The probing interval/guard size can be set by using > + <code>--param stack-clash-protection-guard-size=12|16</code>. > + The value of this parameter must be in bytes represented as a power > of two. > + The only two supported values for this parameter are 12 and 16 being > + 4Kb (2^12) and 64Kb (2^16) respectively. > > This one keeps making me think every time I read it. What do you > think of changing the second and third sentences to > > "The two supported values for this paramter are 12 (for a 4KiB size, > 2^12) and 16 (for a 64KiB size, 2^16)." > > or something like that? Shorter and about the same contents? (Note, > uppercase B or we'd refer to bits.) > > + The Armv8.3-A complex number instructions are now supported via > intrinsics > + when the option <code>-march=armv8.3-a</code> or equivalent is > specified. > + For the half-precision floating-point variants of these instructions > use the > + architecture extension flag <code>+fp16</code>, e.g. > + <code>-march=armv8.3-a+fp16</code>. > + > + The intrinsics are defined by the ACLE specification. > > Note that these two visual paragraphs in HTML source will be merged into > just one unless you add <p>...</p> around the two. Just pointing it out. > > + <li> > + The Armv8.3-A complex number instructions are now supported via > intrinsics > + when the option <code>-march=armv8.3-a</code> or equivalent is > specified. > + For the half-precision floating-point variants of these instructions > use the > + architecture extension flag <code>+fp16</code>, e.g. > + <code>-march=armv8.3-a+fp16</code>. > + > + The intrinsics are defined by the ACLE specification. > + </li> > > I guess this duplication is hard to avoid between Arm and AArch64? > > Gerald >
Hi Gerald, I've updated the patch with your suggested changes and have grouped the Arm and AArch64 targets a bit. Ok for commit? Thanks, Tamar The 01/31/2019 10:21, Ramana Radhakrishnan wrote: > > > On Thu, 31 Jan 2019, 10:09 Tamar Christina <Tamar.Christina@arm.com<mailto:Tamar.Christina@arm.com> wrote: > Hi Gerard, > > Thanks I'll make the suggested changes. > > About the duplication, we can avoid it if we have a "general" section for all Arm ports first and then subsections for Arm and AArch64 specific things. > > I'm not sure how the maintainers feel about such a re-organization though. > > Works for me > > R > > Any opinions guys? > > Thanks, > Tamar > > ________________________________________ > From: Gerald Pfeifer <gerald@pfeifer.com<mailto:gerald@pfeifer.com>> > Sent: Thursday, January 31, 2019 12:29 AM > To: Tamar Christina > Cc: gcc-patches@gcc.gnu.org<mailto:gcc-patches@gcc.gnu.org>; nd; James Greenhalgh; Richard Earnshaw; Marcus Shawcroft; Ramana Radhakrishnan; nickc@redhat.com<mailto:nickc@redhat.com>; Kyrylo Tkachov > Subject: Re: [PATCH][wwwdocs][Arm][AArch64] Update changes with new features and flags. > > On Wed, 23 Jan 2019, Tamar Christina wrote: > > This patch adds the documentation for Stack clash protection and > > Armv8.3-a support to changes.html for GCC 9. > > Some additional notes, all minor, for consideration before you commit. > > + The probing interval/guard size can be set by using > + <code>--param stack-clash-protection-guard-size=12|16</code>. > + The value of this parameter must be in bytes represented as a power of two. > + The only two supported values for this parameter are 12 and 16 being > + 4Kb (2^12) and 64Kb (2^16) respectively. > > This one keeps making me think every time I read it. What do you > think of changing the second and third sentences to > > "The two supported values for this paramter are 12 (for a 4KiB size, > 2^12) and 16 (for a 64KiB size, 2^16)." > > or something like that? Shorter and about the same contents? (Note, > uppercase B or we'd refer to bits.) > > + The Armv8.3-A complex number instructions are now supported via intrinsics > + when the option <code>-march=armv8.3-a</code> or equivalent is specified. > + For the half-precision floating-point variants of these instructions use the > + architecture extension flag <code>+fp16</code>, e.g. > + <code>-march=armv8.3-a+fp16</code>. > + > + The intrinsics are defined by the ACLE specification. > > Note that these two visual paragraphs in HTML source will be merged into > just one unless you add <p>...</p> around the two. Just pointing it out. > > + <li> > + The Armv8.3-A complex number instructions are now supported via intrinsics > + when the option <code>-march=armv8.3-a</code> or equivalent is specified. > + For the half-precision floating-point variants of these instructions use the > + architecture extension flag <code>+fp16</code>, e.g. > + <code>-march=armv8.3-a+fp16</code>. > + > + The intrinsics are defined by the ACLE specification. > + </li> > > I guess this duplication is hard to avoid between Arm and AArch64? > > Gerald -- Index: htdocs/gcc-9/changes.html =================================================================== RCS file: /cvs/gcc/wwwdocs/htdocs/gcc-9/changes.html,v retrieving revision 1.35 diff -u -r1.35 changes.html --- htdocs/gcc-9/changes.html 15 Jan 2019 13:17:49 -0000 1.35 +++ htdocs/gcc-9/changes.html 5 Feb 2019 16:03:46 -0000 @@ -199,7 +199,8 @@ <!-- .................................................................. --> <h2 id="targets">New Targets and Target Specific Improvements</h2> -<h3 id="aarch64">AArch64</h3> +<h3 id="arm-targets">AArch64 & Arm</h3> + <ul> <li> Support has been added for the following processors @@ -214,32 +215,35 @@ <code>-mtune=cortex-a76.cortex-a55</code> or as arguments to the equivalent target attributes and pragmas. </li> + <li> + <p>The Armv8.3-A complex number instructions are now supported via intrinsics + when the option <code>-march=armv8.3-a</code> or equivalent is specified. + For the half-precision floating-point variants of these instructions use the + architecture extension flag <code>+fp16</code>, e.g. + <code>-march=armv8.3-a+fp16</code>. + </p> + <p>The intrinsics are defined by the ACLE specification.</p> + </li> </ul> -<h3 id="arc">ARC</h3> +<h5 id="aarch64">AArch64 specific</h5> <ul> - <li>LRA is now on by default for the ARC target. This can be - controlled by <code>-mlra</code>.</li> - <li>Add support for frame code-density and branch-and-index - instructions.</li> + <li> + The AArch64 port now has support for stack clash protection using the + <code>-fstack-clash-protection</code> option. The probing interval/guard + size can be set by using <code>--param stack-clash-protection-guard-size=12|16</code>. + The value of this parameter must be in bytes represented as a power of two. + The two supported values for this parameter are 12 (for a 4KiB size, 2^12) + and 16 (for a 64KiB size, 2^16). + + The default value is 16 (64Kb) and can be changed at configure + time using the flag <code>--with-stack-clash-protection-guard-size=12|16</code>. + </li> </ul> -<h3 id="arm">Arm</h3> +<h5 id="arm">Arm specific</h5> <ul> <li> - Support has been added for the following processors - (GCC identifiers in parentheses): - <ul> - <li>Arm Cortex-A76 (<code>cortex-a76</code>).</li> - <li>Arm Cortex-A55/Cortex-A76 DynamIQ big.LITTLE (<code>cortex-a76.cortex-a55</code>).</li> - </ul> - The GCC identifiers can be used - as arguments to the <code>-mcpu</code> or <code>-mtune</code> options, - for example: <code>-mcpu=cortex-a76</code> or - <code>-mtune=cortex-a76.cortex-a55</code> or as arguments to the equivalent target - attributes and pragmas. - </li> - <li> Support for the deprecated Armv2 and Armv3 architectures and their variants has been removed. Their corresponding <code>-march</code> values and the <code>-mcpu</code> options that used these architectures @@ -252,6 +256,14 @@ </li> </ul> +<h3 id="arc">ARC</h3> +<ul> + <li>LRA is now on by default for the ARC target. This can be + controlled by <code>-mlra</code>.</li> + <li>Add support for frame code-density and branch-and-index + instructions.</li> +</ul> + <!-- <h3 id="avr">AVR</h3> --> <h3 id="csky">C-SKY</h3>
On Wed, 6 Feb 2019, Tamar Christina wrote: > I've updated the patch with your suggested changes and have grouped > the Arm and AArch64 targets a bit. Thanks, Tamar! > Ok for commit? Yes, I had meant to imply this in my original review. :-) Only note is that this seems to hop from <h3> to <h5>, skipping <h4>? Gerald
Hi Gerard, > > On Wed, 6 Feb 2019, Tamar Christina wrote: > > I've updated the patch with your suggested changes and have grouped > > the Arm and AArch64 targets a bit. > > Thanks, Tamar! > > > Ok for commit? > > Yes, I had meant to imply this in my original review. :-) > > Only note is that this seems to hop from <h3> to <h5>, skipping <h4>? Yeah, the h4 heading was still a bit big, so visually it didn't look quite like a "child" entry. So I skipped on level. Cheers, Tamar > > Gerald
Index: htdocs/gcc-9/changes.html =================================================================== RCS file: /cvs/gcc/wwwdocs/htdocs/gcc-9/changes.html,v retrieving revision 1.35 diff -u -r1.35 changes.html --- htdocs/gcc-9/changes.html 15 Jan 2019 13:17:49 -0000 1.35 +++ htdocs/gcc-9/changes.html 22 Jan 2019 11:16:07 -0000 @@ -214,6 +214,27 @@ <code>-mtune=cortex-a76.cortex-a55</code> or as arguments to the equivalent target attributes and pragmas. </li> + <li> + The AArch64 port now has support for stack clash protection using the + <code>-fstack-clash-protection</code> option. The protection also works for + SVE systems. The probing interval/guard size can be set by using + <code>--param stack-clash-protection-guard-size=12|16</code>. + The value of this parameter must be in bytes represented as a power of two. + The only two supported values for this parameter are 12 and 16 being + 4Kb (2^12) and 64Kb (2^16) respectively. + + The default value is 16 (64Kb) and can be changed at configure + time using the flag <code>--with-stack-clash-protection-guard-size=12|16</code>. + </li> + <li> + The Armv8.3-A complex number instructions are now supported via intrinsics + when the option <code>-march=armv8.3-a</code> or equivalent is specified. + For the half-precision floating-point variants of these instructions use the + architecture extension flag <code>+fp16</code>, e.g. + <code>-march=armv8.3-a+fp16</code>. + + The intrinsics are defined by the ACLE specification. + </li> </ul> <h3 id="arc">ARC</h3> @@ -250,6 +271,15 @@ (which have no known implementations) has been removed. Note that Armv5T, Armv5TE and Armv5TEJ architectures remain supported. </li> + <li> + The Armv8.3-A complex number instructions are now supported via intrinsics + when the option <code>-march=armv8.3-a</code> or equivalent is specified. + For the half-precision floating-point variants of these instructions use the + architecture extension flag <code>+fp16</code>, e.g. + <code>-march=armv8.3-a+fp16</code>. + + The intrinsics are defined by the ACLE specification. + </li> </ul> <!-- <h3 id="avr">AVR</h3> -->