From patchwork Tue Jan 2 20:59:20 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jim Wilson X-Patchwork-Id: 854762 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-470001-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="cq7lfPi7"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3zB5zD3Z5Vz9s9Y for ; Wed, 3 Jan 2018 07:59:34 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id; q=dns; s=default; b=K5EeSZ2ZC4Cz R1hl8SVdChzl8ev+8zgv+rZ1PghSMPgRzS9aQClior2FIlfoyquFNcWLgAziirTD cM2P0Ael5g6Loh8ojurlkiHa7B68QeJYAp7AUqkx91EY8TsOpJ3l2ivF4rgRI9kT NFkf9ZKBEfncDz/gPqHh6HrAbVarMNs= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id; s=default; bh=upokKPCgkfYfUzcMQY mHESYWZNc=; b=cq7lfPi7D7j/SfqJ+Hz6OuYlDpPeqYrQN8uOnvGz6TKIJQpgoW In+E/e1aZTn7CWppxL22VaSSOsaE0lfs9v1VX59KZ4fex2ebk0t/z+K7WT/N7WQr yZ94HOLIB595+/OG76vi8rBB74ZF4joDABCiGM5vsfoM7hohZgM/WIfiM= Received: (qmail 66014 invoked by alias); 2 Jan 2018 20:59:28 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 66002 invoked by uid 89); 2 Jan 2018 20:59:27 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-25.9 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=hart, Hx-languages-length:2016 X-HELO: mail-pf0-f181.google.com Received: from mail-pf0-f181.google.com (HELO mail-pf0-f181.google.com) (209.85.192.181) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 02 Jan 2018 20:59:26 +0000 Received: by mail-pf0-f181.google.com with SMTP id d23so26096157pfe.9 for ; Tue, 02 Jan 2018 12:59:25 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=mPLIBmSVvg6d+klv9yywBuVVFq4mm25plBmo6LdYhLg=; b=jbzXnW8QEh6TwgVa3JFdk7RuKzeNzCwKRB8GH0PKEYgq/YP0X37dDZ95HWGoXu6ADj 6+68eTLm9WyTw0r1nN8Q2D9fehQWC2T8KWp8u5btb7jytSJkishnFKXO2VgBqoWRjZNI kE18BYcdw8xa7lKk87bNSC/kLtaV/FGBS+y9QKLZ66s3uib26Op9qfJ/lIwrY4x6Kz5a DpdPi5BCUTL9DrShBIz/1MLuRvtb8kXseQ7+I0QGnTR8iPrZt6S+gix4rdKqMrdvNKwA joNeo+I6AIC6/4i78geOi9ldBfePDpv5dH3o8qAT8bu4WYpdp+4gdOimDZsFOPN/4H0e pXQA== X-Gm-Message-State: AKGB3mItwOIlJqgQZknWSn16dQ35twGhCXnQWZty2n+tyeLICWeQRNth kUC6/x5hgmj8Rc5QnexpP7eG4DTg20s= X-Google-Smtp-Source: ACJfBot4oNllF7LwmvlBUWOAZ0VYUHGngt6BXUWNDyUDs8hRl6NA5giHPTGBKaV1nvHyPFHxYthcOw== X-Received: by 10.99.119.77 with SMTP id s74mr39516471pgc.82.1514926764122; Tue, 02 Jan 2018 12:59:24 -0800 (PST) Received: from rohan.internal.sifive.com ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id s14sm101768192pfe.36.2018.01.02.12.59.23 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 02 Jan 2018 12:59:23 -0800 (PST) From: Jim Wilson To: gcc-patches@gcc.gnu.org Cc: Jim Wilson Subject: [PATCH] RISC-V: Fix for icache flush issue on multicore processors. Date: Tue, 2 Jan 2018 12:59:20 -0800 Message-Id: <20180102205920.667-1-jimw@sifive.com> The RISC-V ISA defines fence.i as flushing the icache on the current hart (hardware thread, aka core) and not on any other hart. If the linux kernel moves a process to a different hart in between writes to code, and the following fence.i instruction, then the result is indeterminate. To fix this, we need to add a new kernel interface to flush the icache, which is currently implemented as a VDSO. Since the glibc support has not been contributed yet, we need to fix this now before doing so creates a linux ABI change. This was tested with a riscv64 linux make check. Since I'm using a user-mode qemu to test, and user-mode qemu doesn't have VDSO support (yet?) that means every testcase that requires an icache flush is failing. This is a temporary problem that we have to live with for now. Otherwise, there are no regressions. Committed. gcc/ * config/riscv/linux.h (ICACHE_FLUSH_FUNC): New. * config/riscv/riscv.md (clear_cache): Use it. --- gcc/config/riscv/linux.h | 2 ++ gcc/config/riscv/riscv.md | 6 ++++++ 2 files changed, 8 insertions(+) diff --git a/gcc/config/riscv/linux.h b/gcc/config/riscv/linux.h index 6c7e3c4e819..4b2f7b6e1fd 100644 --- a/gcc/config/riscv/linux.h +++ b/gcc/config/riscv/linux.h @@ -45,6 +45,8 @@ along with GCC; see the file COPYING3. If not see #define LIB_SPEC GNU_USER_TARGET_LIB_SPEC " -latomic " #endif +#define ICACHE_FLUSH_FUNC "__riscv_flush_icache" + #define LINK_SPEC "\ -melf" XLEN_SPEC "lriscv \ %{shared} \ diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index db4fed48e53..dab54ad2738 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -1456,7 +1456,13 @@ (match_operand 1 "pmode_register_operand")] "" { +#ifdef ICACHE_FLUSH_FUNC + emit_library_call (gen_rtx_SYMBOL_REF (Pmode, ICACHE_FLUSH_FUNC), + LCT_NORMAL, VOIDmode, operands[0], Pmode, + operands[1], Pmode, const0_rtx, Pmode); +#else emit_insn (gen_fence_i ()); +#endif DONE; })