From patchwork Tue Nov 28 22:17:53 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jim Wilson X-Patchwork-Id: 842342 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-468125-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="BMv+bYIu"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3ymdN36nK4z9ryv for ; Wed, 29 Nov 2017 09:18:08 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id; q=dns; s=default; b=tF+e7JM1i4mU TCNMGgnElSnbzSmEbUS/QRhFhovYEPZgZyVmWpFtlbhzLMstEM55sy2MmdgZbyOW Eq2or6R9ZnEMBOK9dFaz9OZKTBXbymC0fbyYZ4Tw2Gm6cIC3aFih25JZLN14CjQt dVnLKYDSBkhxieIN04qe+dJEyZCWHx0= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id; s=default; bh=1fjDbXVk+l3kKLrwQ0 rVhyoztZk=; b=BMv+bYIuw6j8kbjEXbYC41ycIra9T3AYosRw4ROro22tlQw5+M Y1hUzHS4vqQ3ByiNz1ehnuAtXyR2jak8Wl+3LcgUi5VrtTmq0iBU3LoCaH03hd5c VK5hjnvTC3rCO6T2cUiEDHfBsv2HdibZ9w2ka8uUBH9SuqB6zoWK1F+IU= Received: (qmail 79995 invoked by alias); 28 Nov 2017 22:18:00 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 79985 invoked by uid 89); 28 Nov 2017 22:17:59 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-25.7 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KB_WAM_FROM_NAME_SINGLEWORD, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=viewing, gol X-HELO: mail-pf0-f169.google.com Received: from mail-pf0-f169.google.com (HELO mail-pf0-f169.google.com) (209.85.192.169) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 28 Nov 2017 22:17:57 +0000 Received: by mail-pf0-f169.google.com with SMTP id v26so575062pfl.7 for ; Tue, 28 Nov 2017 14:17:57 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=H+z4DozmVI1Rnqt94C6O7QlmGrM2uU53eq2vb6GOCM0=; b=EmZPAHatQorTnrggqa3xjLBsa8t5IbYufnCArrD9U3Wd8USLVHb1FAJVBeEWItYR7j kZdA4hRR93y3r7RQbDy+T4MQ0bXML5rUiYI9oYW0zIMjR1J9mnZt3kfk4rc9RYJX0XTb SjQ2vUu98hoBcF2sRZRpVZHkG7JQAlNwOvIoe6qUcByyVWXs2Pdl+LT/LYs0j2Jj3MmW pDl44Bp4tVcBteOhloD6B0hEOw6ZRJtzcFpm+HQ+WRW+NJfWcJDdGBGpGfxG/7oM2IYn zRfG9/VJCmNugznGAxNMhnCeRw1Pg12VPbhM8wxLQV33KXB4afL/0vhobzDpvBRNxYtm 1J0Q== X-Gm-Message-State: AJaThX7tgUQvCVKPtvUMIrc9Tb+aF0jsze6raAp/LrdechagHBRJ6Glp DwHSmv6MJzHIOA++ar9X8wkiclZ3swY= X-Google-Smtp-Source: AGs4zMbItIGCT28GsuZ49d2kMSWPFJXELC2cH6nObyzocHLLwJX517WAtVZ5Oo4WGvrmNFz4eUzRGA== X-Received: by 10.99.43.5 with SMTP id r5mr651354pgr.348.1511907476004; Tue, 28 Nov 2017 14:17:56 -0800 (PST) Received: from rohan.internal.sifive.com ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id q68sm156964pfb.180.2017.11.28.14.17.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 28 Nov 2017 14:17:55 -0800 (PST) From: Jim Wilson To: gcc-patches@gcc.gnu.org Cc: Jim Wilson Subject: [PATCH, docs] Cleanup riscv option docs. Date: Tue, 28 Nov 2017 14:17:53 -0800 Message-Id: <20171128221753.11886-1-jimw@sifive.com> This patch fixes a number of issues with the RISC-V option docs. Deletes a non-existent option. Adds missing default value info. Deletes some redundant lines that appear to be from a patch merging error. Adds missing docs for the -mexplicit-relocs option. Tested with a make doc, and viewing the generated gcc.info files to make sure they are OK. I'll wait a few days in case a doc maintainer wants to comment, and then will check it in as is if I don't get any comments. gcc/ * doc/invoke.texi (RISC-V Options): Delete nonexistent -mmemcpy and -mno-memcpy options. For -mplt, -mfdiv, -mdiv, -msave-restore, and -mstrict-align, add info on default value. Delete redundant lines for -mabi. Add missing -mexplicit-relocs docs. --- gcc/doc/invoke.texi | 34 ++++++++++++++++++++-------------- 1 file changed, 20 insertions(+), 14 deletions(-) diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 44273284483..09f935eb194 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -979,7 +979,6 @@ See RS/6000 and PowerPC Options. @emph{RISC-V Options} @gccoptlist{-mbranch-cost=@var{N-instruction} @gol --mmemcpy -mno-memcpy @gol -mplt -mno-plt @gol -mabi=@var{ABI-string} @gol -mfdiv -mno-fdiv @gol @@ -21772,18 +21771,12 @@ These command-line options are defined for RISC-V targets: @opindex mbranch-cost Set the cost of branches to roughly @var{n} instructions. -@item -mmemcpy -@itemx -mno-memcpy -@opindex mmemcpy -Don't optimize block moves. - @item -mplt @itemx -mno-plt @opindex plt -When generating PIC code, allow the use of PLTs. Ignored for non-PIC. +When generating PIC code, do or don't allow the use of PLTs. Ignored for +non-PIC. The default is @option{-mplt}. -@item -mabi=@var{ABI-string} -@opindex mabi @item -mabi=@var{ABI-string} @opindex mabi Specify integer and floating-point calling convention. @var{ABI-string} @@ -21808,13 +21801,16 @@ registers are only 32 bits wide. @item -mfdiv @itemx -mno-fdiv @opindex mfdiv -Use hardware floating-point divide and square root instructions. This requires -the F or D extensions for floating-point registers. +Do or don't use hardware floating-point divide and square root instructions. +This requires the F or D extensions for floating-point registers. The default +is to use them if the specified architecture has these instructions. @item -mdiv @itemx -mno-div @opindex mdiv -Use hardware instructions for integer division. This requires the M extension. +Do or don't use hardware instructions for integer division. This requires the +M extension. The default is to use them if the specified architecture has +these instructions. @item -march=@var{ISA-string} @opindex march @@ -21834,12 +21830,16 @@ Put global and static data smaller than @var{n} bytes into a special section @item -msave-restore @itemx -mno-save-restore @opindex msave-restore -Use smaller but slower prologue and epilogue code. +Do or don't use smaller but slower prologue and epilogue code that uses +library function calls. The default is to use fast inline prologues and +epilogues. @item -mstrict-align @itemx -mno-strict-align @opindex mstrict-align -Do not generate unaligned memory accesses. +Do not or do generate unaligned memory accesses. The default is set depending +on whether the processor we are optimizing for supports fast unaligned access +or not. @item -mcmodel=medlow @opindex mcmodel=medlow @@ -21854,6 +21854,12 @@ Generate code for the medium-any code model. The program and its statically defined symbols must be within any single 2 GiB address range. Programs can be statically or dynamically linked. +@item -mexplicit-relocs +@itemx -mno-exlicit-relocs +Use or do not use assembler relocation operators when dealing with symbolic +addresses. The alternative is to use assembler macros instead, which may +limit optimization. + @end table @node RL78 Options