From patchwork Mon Nov 20 12:50:03 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Cederman X-Patchwork-Id: 839532 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-467411-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="LuzQyTfT"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3ygT9M0G9pz9rxj for ; Mon, 20 Nov 2017 23:51:02 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references; q=dns; s= default; b=CYMO3B7eDPcuJxqZzRDDP7dc9BA+hP5gP5bGjTFOQheamtAtCEzGe nrnwojArziMNWevaWacvxUqhLvBkY6U9ealugJPy09i0pHsLU8t9W+caDpLZB9EF XyuLhPSuAQVUmFRuqWsynOGL079SitYqgRJVEfttTUX7iTZEHg6ap4= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references; s= default; bh=/fPTmiDZL19fxV1taFErbl7QPYw=; b=LuzQyTfTBZRRYA5sLzQr udbDbp/b7hhyXuQgaYGkGIvyJe1W4GGBbfLIE6+gYHY+NVsEt5Rh0Amvuy+iK+O3 wrlaFAgILAc5fUbKZQWZlhKgy2ASXK9CbUDyVAed+GZ7TBtmgZIrKPSCxvdiLUfu KIcg/3jbk0UaU1K4CGNIAQQ= Received: (qmail 5399 invoked by alias); 20 Nov 2017 12:50:21 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 5233 invoked by uid 89); 20 Nov 2017 12:50:20 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-25.7 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_NUMSUBJECT, KB_WAM_FROM_NAME_SINGLEWORD, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 spammy=H*Ad:U*daniel, H*Ad:U*ebotcazou, 94539, symbol_ref X-HELO: bin-vsp-out-03.atm.binero.net Received: from vsp-unauthed02.binero.net (HELO bin-vsp-out-03.atm.binero.net) (195.74.38.227) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 20 Nov 2017 12:50:17 +0000 X-Halon-ID: 59ae9198-cdf1-11e7-811b-0050569116f7 Authorized-sender: cederman@gaisler.com Received: from localhost.localdomain (unknown [81.170.187.120]) by bin-vsp-out-03.atm.binero.net (Halon) with ESMTPA id 59ae9198-cdf1-11e7-811b-0050569116f7; Mon, 20 Nov 2017 13:50:13 +0100 (CET) From: Daniel Cederman To: gcc-patches@gcc.gnu.org Cc: ebotcazou@adacore.com, sebastian.huber@embedded-brains.de, daniel@gaisler.com Subject: [PATCH 4/4] [SPARC] Errata workaround for GRLIB-TN-0013 Date: Mon, 20 Nov 2017 13:50:03 +0100 Message-Id: <20171120125003.22670-5-cederman@gaisler.com> In-Reply-To: <20171120125003.22670-1-cederman@gaisler.com> References: <20171120125003.22670-1-cederman@gaisler.com> X-IsSubscribed: yes This patch provides a workaround for the errata described in GRLIB-TN-0013. If the workaround is enabled it will: * Prevent div and sqrt instructions in the delay slot. * Insert NOPs to prevent the sequence (div/sqrt) -> (two or three floating point operations or loads) -> (div/sqrt). * Not insert NOPs if any of the floating point operations have a dependency on the destination register of the first (div/sqrt). * Not insert NOPs if one of the floating point operations is a (div/sqrt). * Insert NOPs to prevent (div/sqrt) followed by a branch. It is applicable to GR712RC, UT700, and UT699. gcc/ChangeLog: 2017-11-17 Daniel Cederman * config/sparc/sparc.c (fpop_reg_depend_p): New function. (div_sqrt_insn_p): New function. (sparc_do_work_around_errata): Insert NOP instructions to prevent sequences that could trigger the TN-0013 errata for certain LEON3 processors. (pass_work_around_errata::gate): Also test sparc_fix_tn0013. (sparc_option_override): Set sparc_fix_tn0013 appropriately. * config/sparc/sparc.md (fix_tn0013): New attribute. (in_branch_delay): Prevent div and sqrt in delay slot if fix_tn0013. * config/sparc/sparc.opt (sparc_fix_tn0013: New variable. --- gcc/config/sparc/sparc.c | 114 ++++++++++++++++++++++++++++++++++++++++++++- gcc/config/sparc/sparc.md | 7 +++ gcc/config/sparc/sparc.opt | 4 ++ 3 files changed, 123 insertions(+), 2 deletions(-) diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c index 9faf774..3da642e 100644 --- a/gcc/config/sparc/sparc.c +++ b/gcc/config/sparc/sparc.c @@ -945,6 +945,39 @@ mem_ref (rtx x) return NULL_RTX; } +/* True if any of the floating-point instruction's source + registers is the same as the provided register. */ + +static int +fpop_reg_depend_p (rtx_insn *insn, unsigned int reg) +{ + extract_insn (insn); + return (REGNO (recog_data.operand[1]) == reg + || (recog_data.n_operands == 3 + && REGNO (recog_data.operand[2]) == reg)); +} + +/* True if the instruction is floating-point division or + floating-point square-root. */ + +static int +div_sqrt_insn_p (rtx_insn *insn) +{ + if ( GET_CODE (PATTERN (insn)) != SET) + return false; + + switch (get_attr_type (insn)) + { + case TYPE_FPDIVS: + case TYPE_FPSQRTS: + case TYPE_FPDIVD: + case TYPE_FPSQRTD: + return true; + default: + return false; + } +} + /* True if floating-point instruction. */ static int @@ -1064,6 +1097,80 @@ sparc_do_work_around_errata (void) insert_nop = true; } + /* Look for sequences that could trigger the TN-0013 errata. */ + if (sparc_fix_tn0013 + && NONJUMP_INSN_P (insn) + && div_sqrt_insn_p (insn)) + { + int i; + int fp_found = 0; + unsigned int dest_reg; + rtx_insn *after; + + dest_reg = REGNO (SET_DEST (single_set (insn))); + + next = next_active_insn (insn); + if (!next) + break; + + for (after = next, i = 0; i < 4; i++) + { + /* Count floating-point operations. */ + if (i != 3 + && fpop_insn_p (after)) + { + /* If the insn uses the destination register of + the div/sqrt, then it cannot be problematic. */ + if (fpop_reg_depend_p (after, dest_reg)) + break; + fp_found++; + } + + /* Count floating-point loads. */ + if (i != 3 + && (set = single_set (after)) != NULL_RTX + && REG_P (SET_DEST (set)) + && REGNO (SET_DEST (set)) > 31) + { + /* If the insn uses the destination register of + the div/sqrt, then it cannot be problematic. */ + if (REGNO (SET_DEST (set)) == dest_reg) + break; + fp_found++; + } + + /* Check if this is a problematic sequence. */ + if (i > 1 + && fp_found >= 2 + && div_sqrt_insn_p (after)) + { + /* Add extra NOP to prevent second version of + problematic sequence. */ + if (i == 2) + emit_insn_before (gen_nop (), next); + insert_nop = true; + break; + } + + /* No need to scan past a second div/sqrt. */ + if (div_sqrt_insn_p (after)) + break; + + /* Insert NOP before branch. */ + if (i < 3 + && (!NONJUMP_INSN_P (after) + || GET_CODE (PATTERN (after)) == SEQUENCE)) + { + insert_nop = true; + break; + } + + after = next_active_insn (after); + if (!after) + break; + } + } + /* Look for either of these two sequences: Sequence A: @@ -1392,7 +1499,7 @@ public: virtual bool gate (function *) { return sparc_fix_at697f || sparc_fix_ut699 || sparc_fix_b2bst - || sparc_fix_gr712rc; + || sparc_fix_gr712rc || sparc_fix_tn0013; } virtual unsigned int execute (function *) @@ -1762,9 +1869,12 @@ sparc_option_override (void) if (!(target_flags_explicit & MASK_LRA)) target_flags |= MASK_LRA; - /* Enable the back-to-back store errata workaround for LEON3FT. */ + /* Enable applicable errata workarounds for LEON3FT. */ if (sparc_fix_ut699 || sparc_fix_ut700 || sparc_fix_gr712rc) + { sparc_fix_b2bst = 1; + sparc_fix_tn0013 = 1; + } /* Disable FsMULd for the UT699 since it doesn't work correctly. */ if (sparc_fix_ut699) diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md index ef789e2..ec2b476 100644 --- a/gcc/config/sparc/sparc.md +++ b/gcc/config/sparc/sparc.md @@ -430,6 +430,10 @@ (symbol_ref "(sparc_fix_b2bst != 0 ? FIX_B2BST_TRUE : FIX_B2BST_FALSE)")) +(define_attr "fix_tn0013" "false,true" + (symbol_ref "(sparc_fix_tn0013 != 0 + ? FIX_TN0013_TRUE : FIX_TN0013_FALSE)")) + (define_attr "fix_gr712rc" "false,true" (symbol_ref "(sparc_fix_gr712rc != 0 ? FIX_GR712RC_TRUE : FIX_GR712RC_FALSE)")) @@ -581,6 +585,9 @@ (define_attr "in_branch_delay" "false,true" (cond [(eq_attr "type" "uncond_branch,branch,cbcond,uncond_cbcond,call,sibcall,call_no_delay_slot,multi") (const_string "false") + (and (eq_attr "fix_tn0013" "true") + (eq_attr "type" "fpdivs,fpsqrts,fpdivd,fpsqrtd")) + (const_string "false") (and (eq_attr "fix_b2bst" "true") (eq_attr "type" "store,fpstore")) (const_string "false") (and (eq_attr "fix_ut699" "true") (eq_attr "type" "load,sload")) diff --git a/gcc/config/sparc/sparc.opt b/gcc/config/sparc/sparc.opt index 22267f5..43cd964 100644 --- a/gcc/config/sparc/sparc.opt +++ b/gcc/config/sparc/sparc.opt @@ -253,6 +253,10 @@ Enable workarounds for the errata of the GR712RC processor. TargetVariable unsigned int sparc_fix_b2bst +;; Enable workaround for TN-0013 errata +TargetVariable +unsigned int sparc_fix_tn0013 + Mask(LONG_DOUBLE_128) ;; Use 128-bit long double