From patchwork Fri Dec 30 20:54:54 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Meissner X-Patchwork-Id: 709870 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3tqzJH0dDSz9t2C for ; Sat, 31 Dec 2016 07:55:22 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="iS5Q1V1Q"; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:subject:mime-version:content-type:message-id; q=dns; s= default; b=e263297z4B0SQKVLpujCkN1tk7Q9c653yy/sLnPx6LzbwXkCi9iSv /tG+o1h4vuM0nGaExBNPOwF34Ax7gaoV2qK2VTng0ehJOmjETrLkwsZv50MN3SoR b1bNJG12so8B28eGaQDUwHIK9L6jLkb861jckkkfFMg0tXaz3W+YnU= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:subject:mime-version:content-type:message-id; s= default; bh=fCu2pVM9bgxK6ygO8Bxi0JYvtxQ=; b=iS5Q1V1Q5g+NRRXD7+GQ tX4Ze+Mpt/6IYcI+c4Oyji1iGz0jqWTIk8YqOUVwPgfKAOFzRtbvXtxFVia1lokI 1qc7icHZE+jq/zSS5n8d/06O8kgwXRBIFS1iZ/waZZwNzS6W/M0eRX+7Kt9LwAAH kb3IujGlGg/2+dObgysQx0g= Received: (qmail 63726 invoked by alias); 30 Dec 2016 20:55:15 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 63238 invoked by uid 89); 30 Dec 2016 20:55:13 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=1.8 required=5.0 tests=AWL, BAYES_50, KAM_ASCII_DIVIDERS, KAM_LAZY_DOMAIN_SECURITY, RCVD_IN_DNSWL_LOW autolearn=no version=3.3.2 spammy=King, burn, littleton, 2506r X-HELO: mx0a-001b2d01.pphosted.com Received: from mx0a-001b2d01.pphosted.com (HELO mx0a-001b2d01.pphosted.com) (148.163.156.1) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 30 Dec 2016 20:55:03 +0000 Received: from pps.filterd (m0098393.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.17/8.16.0.17) with SMTP id uBUKmcJt137245 for ; Fri, 30 Dec 2016 15:55:01 -0500 Received: from e35.co.us.ibm.com (e35.co.us.ibm.com [32.97.110.153]) by mx0a-001b2d01.pphosted.com with ESMTP id 27nucrrcte-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Fri, 30 Dec 2016 15:55:00 -0500 Received: from localhost by e35.co.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Fri, 30 Dec 2016 13:54:56 -0700 Received: from b03cxnp08028.gho.boulder.ibm.com (b03cxnp08028.gho.boulder.ibm.com [9.17.130.20]) by d03dlp03.boulder.ibm.com (Postfix) with ESMTP id AD23519D8026; Fri, 30 Dec 2016 13:54:13 -0700 (MST) Received: from b03ledav002.gho.boulder.ibm.com (b03ledav002.gho.boulder.ibm.com [9.17.130.233]) by b03cxnp08028.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id uBUKsupn7143898; Fri, 30 Dec 2016 13:54:56 -0700 Received: from b03ledav002.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 3EF13136044; Fri, 30 Dec 2016 13:54:56 -0700 (MST) Received: from ibm-tiger.the-meissners.org (unknown [9.32.77.111]) by b03ledav002.gho.boulder.ibm.com (Postfix) with ESMTP id 1E23913603A; Fri, 30 Dec 2016 13:54:56 -0700 (MST) Received: by ibm-tiger.the-meissners.org (Postfix, from userid 500) id 62B654730B; Fri, 30 Dec 2016 15:54:55 -0500 (EST) Date: Fri, 30 Dec 2016 15:54:54 -0500 From: Michael Meissner To: gcc-patches@gcc.gnu.org, Segher Boessenkool , David Edelsohn , Bill Schmidt Subject: [PATCH], PR target/78900, Fix PowerPC __float128 signbit Mail-Followup-To: Michael Meissner , gcc-patches@gcc.gnu.org, Segher Boessenkool , David Edelsohn , Bill Schmidt MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.5.20 (2009-12-10) X-TM-AS-GCONF: 00 X-Content-Scanned: Fidelis XPS MAILER x-cbid: 16123020-0012-0000-0000-000012D7E5B2 X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00006345; HX=3.00000240; KW=3.00000007; PH=3.00000004; SC=3.00000199; SDB=6.00801330; UDB=6.00389520; IPR=6.00579152; BA=6.00005019; NDR=6.00000001; ZLA=6.00000005; ZF=6.00000009; ZB=6.00000000; ZP=6.00000000; ZH=6.00000000; ZU=6.00000002; MB=3.00013772; XFM=3.00000011; UTC=2016-12-30 20:54:58 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 16123020-0013-0000-0000-000049BCDC93 Message-Id: <20161230205454.GA25347@ibm-tiger.the-meissners.org> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2016-12-30_14:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1612050000 definitions=main-1612300324 X-IsSubscribed: yes The signbit-3.c test explicitly tests for the value coming from memory, a vector register, or a GPR. Unfortunately, the code did not handle splitting up the registers when the value was in a GPR. These patches add teh GPR support. While I was editing the code, I also did some cleanup. I removed the Fsignbit mode attribute, since the only two modes used both use the same attribute. This is a relic of the original code generation that also provided optimized signbit support for DFmode/SFmode. Since the DFmode/SFmode got dropped (GCC 6 was in stage 3, and we needed to get signbit working for __float128 -- it already worked for DFmode/SFmode, but the code generation could be improved). I also noticed that use of signbit tended to generate sign or zero extension. Since the function only returns 0/1, I added combiner insns to eliminate the extra zero/sign extend. I have tested this on both big endian and little endian power8 systems. The bootstrap and make check had no regressions. Is this ok to put into the trunk? The same error appears on GCC 6 as well. Assuming the patch applys cleanly and fixes the problem, can I install it on the GCC 6 branch as well after a burn in period? 2016-12-30 Michael Meissner PR target/78900 * config/rs6000/rs6000.c (rs6000_split_signbit): Change some assertions. Add support for doing the signbit if the IEEE 128-bit floating point value is in a GPR. * config/rs6000/rs6000.md (Fsignbit): Delete. (signbit2_dm): Delete using and just use "wa". Update the length attribute if the value is in a GPR. (signbit2_dm_ext): Add combiner pattern to eliminate the sign or zero extension instruction, since the value is always 0/1. (signbit2_dm2): Delete using . Index: gcc/config/rs6000/rs6000.c =================================================================== --- gcc/config/rs6000/rs6000.c (revision 243966) +++ gcc/config/rs6000/rs6000.c (working copy) @@ -25170,9 +25170,7 @@ rs6000_split_signbit (rtx dest, rtx src) rtx dest_di = (d_mode == DImode) ? dest : gen_lowpart (DImode, dest); rtx shift_reg = dest_di; - gcc_assert (REG_P (dest)); - gcc_assert (REG_P (src) || MEM_P (src)); - gcc_assert (s_mode == KFmode || s_mode == TFmode); + gcc_assert (FLOAT128_IEEE_P (s_mode) && TARGET_POWERPC64); if (MEM_P (src)) { @@ -25184,17 +25182,20 @@ rs6000_split_signbit (rtx dest, rtx src) else { - unsigned int r = REGNO (src); + unsigned int r = reg_or_subregno (src); - /* If this is a VSX register, generate the special mfvsrd instruction - to get it in a GPR. Until we support SF and DF modes, that will - always be true. */ - gcc_assert (VSX_REGNO_P (r)); + if (INT_REGNO_P (r)) + shift_reg = gen_rtx_REG (DImode, r + (BYTES_BIG_ENDIAN == 0)); - if (s_mode == KFmode) - emit_insn (gen_signbitkf2_dm2 (dest_di, src)); else - emit_insn (gen_signbittf2_dm2 (dest_di, src)); + { + /* Generate the special mfvsrd instruction to get it in a GPR. */ + gcc_assert (VSX_REGNO_P (r)); + if (s_mode == KFmode) + emit_insn (gen_signbitkf2_dm2 (dest_di, src)); + else + emit_insn (gen_signbittf2_dm2 (dest_di, src)); + } } emit_insn (gen_lshrdi3 (dest_di, shift_reg, GEN_INT (63))); Index: gcc/config/rs6000/rs6000.md =================================================================== --- gcc/config/rs6000/rs6000.md (revision 243966) +++ gcc/config/rs6000/rs6000.md (working copy) @@ -518,9 +518,6 @@ (define_mode_iterator FLOAT128 [(KF "TAR (define_mode_iterator SIGNBIT [(KF "FLOAT128_VECTOR_P (KFmode)") (TF "FLOAT128_VECTOR_P (TFmode)")]) -(define_mode_attr Fsignbit [(KF "wa") - (TF "wa")]) - ; Iterator for ISA 3.0 supported floating point types (define_mode_iterator FP_ISA3 [SF DF @@ -4744,7 +4741,7 @@ (define_expand "copysign3" (define_insn_and_split "signbit2_dm" [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") (unspec:SI - [(match_operand:SIGNBIT 1 "input_operand" ",m,r")] + [(match_operand:SIGNBIT 1 "input_operand" "wa,m,r")] UNSPEC_SIGNBIT))] "TARGET_POWERPC64 && TARGET_DIRECT_MOVE" "#" @@ -4754,7 +4751,24 @@ (define_insn_and_split "signbit2_d rs6000_split_signbit (operands[0], operands[1]); DONE; } - [(set_attr "length" "8,8,12") + [(set_attr "length" "8,8,4") + (set_attr "type" "mftgpr,load,integer")]) + +(define_insn_and_split "*signbit2_dm_ext" + [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r") + (any_extend:DI + (unspec:SI + [(match_operand:SIGNBIT 1 "input_operand" "wa,m,r")] + UNSPEC_SIGNBIT)))] + "TARGET_POWERPC64 && TARGET_DIRECT_MOVE" + "#" + "&& reload_completed" + [(const_int 0)] +{ + rs6000_split_signbit (operands[0], operands[1]); + DONE; +} + [(set_attr "length" "8,8,4") (set_attr "type" "mftgpr,load,integer")]) ;; MODES_TIEABLE_P doesn't allow DImode to be tied with the various floating @@ -4762,7 +4776,7 @@ (define_insn_and_split "signbit2_d ;; special pattern to avoid using a normal movdi. (define_insn "signbit2_dm2" [(set (match_operand:DI 0 "gpc_reg_operand" "=r") - (unspec:DI [(match_operand:SIGNBIT 1 "gpc_reg_operand" "") + (unspec:DI [(match_operand:SIGNBIT 1 "gpc_reg_operand" "wa") (const_int 0)] UNSPEC_SIGNBIT))] "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"