From patchwork Tue Sep 20 12:38:41 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dominik Vogt X-Patchwork-Id: 672245 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3sdj4Z1gNmz9sQw for ; Tue, 20 Sep 2016 22:39:26 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=UvvlWyTq; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:subject:reply-to:references:mime-version:content-type :in-reply-to:message-id; q=dns; s=default; b=RUoAIrPLJsGfSHMBw3O nTiyxEUHLdMBwXwUvA5Lg5MRvO0ZJtaA6bAaoEHE/UKJMtg8n9WD5E+TMTXGwWno GOHMMlTOZ+j+hBlZ6Qjo013uA/DTrZYiCiilI+XFManSQfyyi3K3rzTR9io5IZ/B QFcvrD3q4y9ihktDpCJUlLfs= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:subject:reply-to:references:mime-version:content-type :in-reply-to:message-id; s=default; bh=DqcJsnd31/JF3JWfTJHB2VjSe 48=; b=UvvlWyTqkOwGajBDOK/kaqoT+AwBN74E8iM6xC+9ftVOZOeqdvf31rspu LycOiabRNWLZMj9AnPUrNbw2TrTVDRFG/9SvskP3e+7f67REoO/lSwGivrXOuXpv SeQOnLkN7i7QanE94haAtKSr5urZ3wqZzMDGRhE/yVNUOZJBDY= Received: (qmail 88905 invoked by alias); 20 Sep 2016 12:39:16 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 88853 invoked by uid 89); 20 Sep 2016 12:39:15 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.6 required=5.0 tests=BAYES_00, KAM_LAZY_DOMAIN_SECURITY, RCVD_IN_DNSWL_LOW autolearn=no version=3.3.2 spammy=ciao, define_insn, risbgn, Spec2006 X-HELO: mx0a-001b2d01.pphosted.com Received: from mx0b-001b2d01.pphosted.com (HELO mx0a-001b2d01.pphosted.com) (148.163.158.5) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 20 Sep 2016 12:39:05 +0000 Received: from pps.filterd (m0098420.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.17/8.16.0.17) with SMTP id u8KCcwKD120497 for ; Tue, 20 Sep 2016 08:39:03 -0400 Received: from e06smtp12.uk.ibm.com (e06smtp12.uk.ibm.com [195.75.94.108]) by mx0b-001b2d01.pphosted.com with ESMTP id 25jmr0jpe4-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Tue, 20 Sep 2016 08:39:02 -0400 Received: from localhost by e06smtp12.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Reply-To: vogt@linux.vnet.ibm.com Mail-Followup-To: vogt@linux.vnet.ibm.com, gcc-patches@gcc.gnu.org, Andreas Krebbel References: <20160920123718.GA26830@linux.vnet.ibm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20160920123718.GA26830@linux.vnet.ibm.com> User-Agent: Mutt/1.5.20 (2009-12-10) X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 16092012-0008-0000-0000-000002CEADCC X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 16092012-0009-0000-0000-00001A072D39 Message-Id: <20160920123841.GA28823@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2016-09-20_05:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1609020000 definitions=main-1609200163 On Tue, Sep 20, 2016 at 01:37:18PM +0100, Dominik Vogt wrote: > The following series of patches improves usage of the risbg and > risbgn instructions on s390/s390x. The patches have been > regression tested on s390 and s390x and pass the Spec2006 > testsuite without any negative effects. > Patch 1 introduces a new mode attribute to simplify some > instruction patterns. Ciao Dominik ^_^ ^_^ diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md index 30ddc14..21ff33e 100644 --- a/gcc/config/s390/s390.md +++ b/gcc/config/s390/s390.md @@ -761,6 +761,9 @@ ;; In place of GET_MODE_BITSIZE (mode) (define_mode_attr bitsize [(DI "64") (SI "32") (HI "16") (QI "8")]) +;; 64 - bitsize +(define_mode_attr bitoff [(DI "0") (SI "32") (HI "48") (QI "56")]) +(define_mode_attr bitoff_plus [(DI "") (SI "32+") (HI "48+") (QI "56+")]) ;; In place of GET_MODE_SIZE (mode) (define_mode_attr modesize [(DI "8") (SI "4")]) @@ -3754,7 +3757,7 @@ (match_operand 2 "const_int_operand" "") ; size (match_operand 3 "const_int_operand" "")))] ; start] "TARGET_ZEC12" - "risbgn\t%0,%1,64-%2,128+63,+%3+%2" ; dst, src, start, end, shift + "risbgn\t%0,%1,64-%2,128+63,%3+%2" ; dst, src, start, end, shift [(set_attr "op_type" "RIE")]) (define_insn "*extzv_z10" @@ -3846,7 +3849,7 @@ (match_operand:GPR 3 "nonimmediate_operand" "d"))] "TARGET_ZEC12 && (INTVAL (operands[1]) + INTVAL (operands[2])) <= " - "risbgn\t%0,%3,64-+%2,64-+%2+%1-1,-%2-%1" + "risbgn\t%0,%3,%2,%2+%1-1,-%2-%1" [(set_attr "op_type" "RIE")]) (define_insn "*insv_z10" @@ -3857,7 +3860,7 @@ (clobber (reg:CC CC_REGNUM))] "TARGET_Z10 && (INTVAL (operands[1]) + INTVAL (operands[2])) <= " - "risbg\t%0,%3,64-+%2,64-+%2+%1-1,-%2-%1" + "risbg\t%0,%3,%2,%2+%1-1,-%2-%1" [(set_attr "op_type" "RIE") (set_attr "z10prop" "z10_super_E1")]) @@ -3894,7 +3897,7 @@ (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "d") (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))] "TARGET_ZEC12 && UINTVAL (operands[2]) == (1UL << UINTVAL (operands[4])) - 1" - "risbgn\t%0,%3,64-,64-%4-1,%4" + "risbgn\t%0,%3,,64-%4-1,%4" [(set_attr "op_type" "RIE") (set_attr "z10prop" "z10_super_E1")]) @@ -3906,7 +3909,7 @@ (match_operand:GPR 4 "nonzero_shift_count_operand" "")))) (clobber (reg:CC CC_REGNUM))] "TARGET_Z10 && !TARGET_ZEC12 && UINTVAL (operands[2]) == (1UL << UINTVAL (operands[4])) - 1" - "risbg\t%0,%3,64-,64-%4-1,%4" + "risbg\t%0,%3,,64-%4-1,%4" [(set_attr "op_type" "RIE") (set_attr "z10prop" "z10_super_E1")]) @@ -4035,7 +4038,7 @@ (match_operand:GPR 3 "nonimmediate_operand" "0"))) (clobber (reg:CC CC_REGNUM))] "TARGET_Z10" - "rsbg\t%0,%1,64-,63-%2,%2" + "rsbg\t%0,%1,,63-%2,%2" [(set_attr "op_type" "RIE")]) ;; unsigned {int,long} a, b @@ -4050,7 +4053,7 @@ (match_operand:GPR 3 "nonimmediate_operand" "0"))) (clobber (reg:CC CC_REGNUM))] "TARGET_Z10" - "rsbg\t%0,%1,64-+%2,63,64-%2" + "rsbg\t%0,%1,%2,63,64-%2" [(set_attr "op_type" "RIE")]) ;; These two are generated by combine for s.bf &= val. diff --git a/gcc/testsuite/gcc.target/s390/md/rXsbg_mode_sXl.c b/gcc/testsuite/gcc.target/s390/md/rXsbg_mode_sXl.c index 178a537..ad442da 100644 --- a/gcc/testsuite/gcc.target/s390/md/rXsbg_mode_sXl.c +++ b/gcc/testsuite/gcc.target/s390/md/rXsbg_mode_sXl.c @@ -39,28 +39,28 @@ rosbg_si_sll (unsigned int a, unsigned int b) { return a | (b << 1); } -/* { dg-final { scan-assembler-times "rosbg\t%r.,%r.,64-32,63-1,1" 1 } } */ +/* { dg-final { scan-assembler-times "rosbg\t%r.,%r.,32,63-1,1" 1 } } */ __attribute__ ((noinline)) unsigned int rosbg_si_srl (unsigned int a, unsigned int b) { return a | (b >> 2); } -/* { dg-final { scan-assembler-times "rosbg\t%r.,%r.,64-32\\+2,63,64-2" 1 } } */ +/* { dg-final { scan-assembler-times "rosbg\t%r.,%r.,32\\+2,63,64-2" 1 } } */ __attribute__ ((noinline)) unsigned int rxsbg_si_sll (unsigned int a, unsigned int b) { return a ^ (b << 1); } -/* { dg-final { scan-assembler-times "rxsbg\t%r.,%r.,64-32,63-1,1" 1 } } */ +/* { dg-final { scan-assembler-times "rxsbg\t%r.,%r.,32,63-1,1" 1 } } */ __attribute__ ((noinline)) unsigned int rxsbg_si_srl (unsigned int a, unsigned int b) { return a ^ (b >> 2); } -/* { dg-final { scan-assembler-times "rxsbg\t%r.,%r.,64-32\\+2,63,64-2" 1 } } */ +/* { dg-final { scan-assembler-times "rxsbg\t%r.,%r.,32\\+2,63,64-2" 1 } } */ __attribute__ ((noinline)) unsigned long long di_sll (unsigned long long x) @@ -79,28 +79,28 @@ rosbg_di_sll (unsigned long long a, unsigned long long b) { return a | (b << 1); } -/* { dg-final { scan-assembler-times "rosbg\t%r.,%r.,64-64,63-1,1" 1 } } */ +/* { dg-final { scan-assembler-times "rosbg\t%r.,%r.,0,63-1,1" 1 } } */ __attribute__ ((noinline)) unsigned long long rosbg_di_srl (unsigned long long a, unsigned long long b) { return a | (b >> 2); } -/* { dg-final { scan-assembler-times "rosbg\t%r.,%r.,64-64\\+2,63,64-2" 1 } } */ +/* { dg-final { scan-assembler-times "rosbg\t%r.,%r.,2,63,64-2" 1 } } */ __attribute__ ((noinline)) unsigned long long rxsbg_di_sll (unsigned long long a, unsigned long long b) { return a ^ (b << 1); } -/* { dg-final { scan-assembler-times "rxsbg\t%r.,%r.,64-64,63-1,1" 1 } } */ +/* { dg-final { scan-assembler-times "rxsbg\t%r.,%r.,0,63-1,1" 1 } } */ __attribute__ ((noinline)) unsigned long long rxsbg_di_srl (unsigned long long a, unsigned long long b) { return a ^ (b >> 2); } -/* { dg-final { scan-assembler-times "rxsbg\t%r.,%r.,64-64\\+2,63,64-2" 1 } } */ +/* { dg-final { scan-assembler-times "rxsbg\t%r.,%r.,2,63,64-2" 1 } } */ int main (void)