From patchwork Wed Jun 29 21:58:37 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Meissner X-Patchwork-Id: 642246 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3rfxQZ0Sqvz9sC3 for ; Thu, 30 Jun 2016 07:59:01 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=Vl1UZvnm; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:subject:mime-version:content-type:message-id; q=dns; s= default; b=S38bQMxgyTsUrebd0WQR671aNleO6vh1u74RiQ8g2M7WQRuaxa46O DuL/vm98672Li06gAtyar+cJVgrCsBj/DhF/WIVot6DkOGUvez5uFqKdB5VQxv7c Tr3gGEp8naJ1gujrXKK5haqEUV4v6RjVcbYy98NfmorzJjf0njBLG0= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:subject:mime-version:content-type:message-id; s= default; bh=ljHf9EdnaAEjR2ZFy9vAw3MXWI8=; b=Vl1UZvnms0vSgSEiDJ2q znVRWRCvg5rwThP5LFLScsHiWCNmL8vT5alroZkhMPCFY0H73mHLMkQH5zcnQl2M TEjYC9kgHVQlo0QeH7z7rECodxM+zclrCJB07kiFXCDg8wXM07+T3S2p1S5rG5P6 i8UVD7INphr36qmQa0awDIw= Received: (qmail 33677 invoked by alias); 29 Jun 2016 21:58:55 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 33657 invoked by uid 89); 29 Jun 2016 21:58:54 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=0.2 required=5.0 tests=AWL, BAYES_00, KAM_ASCII_DIVIDERS, KAM_LAZY_DOMAIN_SECURITY, RCVD_IN_DNSWL_LOW autolearn=no version=3.3.2 spammy=gpc_reg_operand, sk:nonimme, match_test, 67738 X-HELO: mx0a-001b2d01.pphosted.com Received: from mx0a-001b2d01.pphosted.com (HELO mx0a-001b2d01.pphosted.com) (148.163.156.1) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-SHA encrypted) ESMTPS; Wed, 29 Jun 2016 21:58:44 +0000 Received: from pps.filterd (m0098410.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.11/8.16.0.11) with SMTP id u5TLroFu016555 for ; Wed, 29 Jun 2016 17:58:42 -0400 Received: from e32.co.us.ibm.com (e32.co.us.ibm.com [32.97.110.150]) by mx0a-001b2d01.pphosted.com with ESMTP id 23uwnmu0kd-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Wed, 29 Jun 2016 17:58:41 -0400 Received: from localhost by e32.co.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Wed, 29 Jun 2016 15:58:39 -0600 X-IBM-Helo: d03dlp03.boulder.ibm.com X-IBM-MailFrom: meissner@ibm-tiger.the-meissners.org Received: from b01cxnp23033.gho.pok.ibm.com (b01cxnp23033.gho.pok.ibm.com [9.57.198.28]) by d03dlp03.boulder.ibm.com (Postfix) with ESMTP id 96FBD19D803F; Wed, 29 Jun 2016 15:58:16 -0600 (MDT) Received: from b01ledav002.gho.pok.ibm.com (b01ledav002.gho.pok.ibm.com [9.57.199.107]) by b01cxnp23033.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id u5TLwdrA38535328; Wed, 29 Jun 2016 21:58:39 GMT Received: from b01ledav002.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 37B34124049; Wed, 29 Jun 2016 17:58:38 -0400 (EDT) Received: from ibm-tiger.the-meissners.org (unknown [9.32.77.111]) by b01ledav002.gho.pok.ibm.com (Postfix) with ESMTP id 12EBA124035; Wed, 29 Jun 2016 17:58:38 -0400 (EDT) Received: by ibm-tiger.the-meissners.org (Postfix, from userid 500) id 6EE8D45D0E; Wed, 29 Jun 2016 17:58:37 -0400 (EDT) Date: Wed, 29 Jun 2016 17:58:37 -0400 From: Michael Meissner To: gcc-patches@gcc.gnu.org, Segher Boessenkool , David Edelsohn , Bill Schmidt Subject: [PATCH], Fix PowerPC bug 71677, make xalancbmk build in Spec 2006 Mail-Followup-To: Michael Meissner , gcc-patches@gcc.gnu.org, Segher Boessenkool , David Edelsohn , Bill Schmidt MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.5.20 (2009-12-10) X-TM-AS-GCONF: 00 X-Content-Scanned: Fidelis XPS MAILER x-cbid: 16062921-0004-0000-0000-00000FCE24C2 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 16062921-0005-0000-0000-000076A3FF90 Message-Id: <20160629215837.GA5407@ibm-tiger.the-meissners.org> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2016-06-29_11:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1604210000 definitions=main-1606290202 X-IsSubscribed: yes Sigh, I forgot to attach the patch, and I also used the wrong bug number in my previous patch. As we discussed in the patch review, there were some issues with using %Y for the ISA 3.0 instructions LXSD and STXSD. I have rewritten the patch so that we have a new memory constraint (%wY) that explicitly targets those instructions. I went back to the mov{DF,DD} patterns and changed their use of %o to %wY. I removed the test that was generated from the XalanNamespacesStack.cpp source that showed up the problem. I have bootstrapped this on a little endian power8 system and there were no regressions in the test suite. I also built Spec 2006 for power9 with this compiler, and the xalancbmk benchmark now builds. I will kick off a big endian build on a power7 system. Assuming there are no regressions in power7, are these patches ok to install in the trunk, and backport to GCC 6.2 after a burn-in period? 2016-06-29 Michael Meissner PR target/71677 * config/rs6000/constraints.md (wY constraint): New constraint to match the requirements for the LXSD and STXSD instructions. * config/rs6000/predicates.md (offsettable_mem_14bit_operand): New predicate to match the requirements for the LXSD and STXSD instructions. * config/rs6000/rs6000.md (mov_hardfloat32, FMOVE64 case): Use constaint wY for LXSD/STXSD instructions instead of 'o' or 'Y' to make sure that the bottom 2 bits of offset are 0, the address form is offsettable, and no updating is done in the address mode. (mov_hardfloat64, FMOVE64 case): Likewise. (movdi_internal32): Likewise (movdi_internal64): Likewise. Index: gcc/config/rs6000/constraints.md =================================================================== --- gcc/config/rs6000/constraints.md (revision 237826) +++ gcc/config/rs6000/constraints.md (working copy) @@ -185,6 +185,11 @@ (define_constraint "wS" "Vector constant that can be loaded with XXSPLTIB & sign extension." (match_test "xxspltib_constant_split (op, mode)")) +;; ISA 3.0 D-form instruction that has the bottom 2 bits 0 (LXSD or STXSD). +(define_memory_constraint "wY" + "Offsettable memory operand, with bottom 2 bits 0" + (match_operand 0 "offsettable_mem_14bit_operand")) + ;; Altivec style load/store that ignores the bottom bits of the address (define_memory_constraint "wZ" "Indexed or indirect memory operand, ignoring the bottom 4 bits" Index: gcc/config/rs6000/predicates.md =================================================================== --- gcc/config/rs6000/predicates.md (revision 237826) +++ gcc/config/rs6000/predicates.md (working copy) @@ -729,6 +729,15 @@ (define_predicate "offsettable_mem_opera (and (match_operand 0 "memory_operand") (match_test "offsettable_nonstrict_memref_p (op)"))) +;; Return 1 if the operand is an offsettable memory operand for ISA 3.0 +;; scalar LXSD/STXSD that must have the bottom 2 bits 0 and no update +;; form +(define_predicate "offsettable_mem_14bit_operand" + (and (match_operand 0 "memory_operand") + (match_test "offsettable_nonstrict_memref_p (op)") + (match_test "mem_operand_gpr (op, mode)") + (not (match_test "update_address_mem (op, mode)")))) + ;; Return 1 if the operand is suitable for load/store quad memory. ;; This predicate only checks for non-atomic loads/stores (not lqarx/stqcx). (define_predicate "quad_memory_operand" Index: gcc/config/rs6000/rs6000.md =================================================================== --- gcc/config/rs6000/rs6000.md (revision 237826) +++ gcc/config/rs6000/rs6000.md (working copy) @@ -6773,8 +6773,8 @@ (define_split ;; except for 0.0 which can be created on VSX with an xor instruction. (define_insn "*mov_hardfloat32" - [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,,Z,,o,,,!r,Y,r,!r") - (match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,,o,,,,,r,Y,r"))] + [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,,Z,,wY,,,!r,Y,r,!r") + (match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,,wY,,,,,r,Y,r"))] "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && (gpc_reg_operand (operands[0], mode) || gpc_reg_operand (operands[1], mode))" @@ -6812,8 +6812,8 @@ (define_insn "*mov_softfloat32" ; ld/std require word-aligned displacements -> 'Y' constraint. ; List Y->r and r->Y before r->r for reload. (define_insn "*mov_hardfloat64" - [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,,o,,Z,,,!r,Y,r,!r,*c*l,!r,*h,r,wg,r,") - (match_operand:FMOVE64 1 "input_operand" "d,m,d,o,,Z,,,,,r,Y,r,r,h,0,wg,r,,r"))] + [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,,wY,,Z,,,!r,Y,r,!r,*c*l,!r,*h,r,wg,r,") + (match_operand:FMOVE64 1 "input_operand" "d,m,d,wY,,Z,,,,,r,Y,r,r,h,0,wg,r,,r"))] "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && (gpc_reg_operand (operands[0], mode) || gpc_reg_operand (operands[1], mode))" @@ -7854,13 +7854,13 @@ (define_insn "p8_mfvsrd_4_disf" (define_insn "*movdi_internal32" [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "=Y, r, r, ?m, ?*d, ?*d, - r, ?Y, ?Z, ?*wb, ?*wv, ?wi, + r, ?wY, ?Z, ?*wb, ?*wv, ?wi, ?wo, ?wo, ?wv, ?wi, ?wi, ?wv, ?wv") (match_operand:DI 1 "input_operand" "r, Y, r, d, m, d, - IJKnGHF, wb, wv, Y, Z, wi, + IJKnGHF, wb, wv, wY, Z, wi, Oj, wM, OjwM, Oj, wM, wS, wB"))] @@ -7930,14 +7930,14 @@ (define_split (define_insn "*movdi_internal64" [(set (match_operand:DI 0 "nonimmediate_operand" "=Y, r, r, r, r, r, - ?m, ?*d, ?*d, ?Y, ?Z, ?*wb, + ?m, ?*d, ?*d, ?wY, ?Z, ?*wb, ?*wv, ?wi, ?wo, ?wo, ?wv, ?wi, ?wi, ?wv, ?wv, r, *h, *h, ?*r, ?*wg, ?*r, ?*wj") (match_operand:DI 1 "input_operand" "r, Y, r, I, L, nF, - d, m, d, wb, wv, Y, + d, m, d, wb, wv, wY, Z, wi, Oj, wM, OjwM, Oj, wM, wS, wB, *h, r, 0, wg, r, wj, r"))]