| Message ID | 20160530134649.GB62543@msticlxl57.ims.intel.com |
|---|---|
| State | New |
| Headers | show |
On Mon, May 30, 2016 at 04:46:50PM +0300, Kirill Yukhin wrote: > Hello, > Patch limits constraint for scalar operand in split to AVX-512VL. > > Boostrap/regtest in progress for x86_64/ia32. > > I'll check it in if pass. > > PR target/71346. > gcc/ > * config/i386/sse.md (define_insn_and_split "*vec_extractv4sf_0"): Use > `Yv' for scalar operand. > testsuite/ > * gcc.target/i386/prr71346.c: New test. Too many `r' chars above. LGTM otherwise and sorry for introducing this in r235970. > commit 6c0021bea7a5be8d9a10ef3f2fb30c1228f53d48 > Author: Kirill Yukhin <kirill.yukhin@intel.com> > Date: Mon May 30 16:31:28 2016 +0300 > > AVX-512. Fix PR target/71346. > > diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md > index b348f2d..1267897 100644 > --- a/gcc/config/i386/sse.md > +++ b/gcc/config/i386/sse.md > @@ -6837,7 +6837,7 @@ > "operands[1] = gen_lowpart (SFmode, operands[1]);") > > (define_insn_and_split "*sse4_1_extractps" > - [(set (match_operand:SF 0 "nonimmediate_operand" "=rm,rm,rm,v,v") > + [(set (match_operand:SF 0 "nonimmediate_operand" "=rm,rm,rm,Yv,Yv") > (vec_select:SF > (match_operand:V4SF 1 "register_operand" "Yr,*x,v,0,v") > (parallel [(match_operand:SI 2 "const_0_to_3_operand" "n,n,n,n,n")])))] > diff --git a/gcc/testsuite/gcc.target/i386/pr71346.c b/gcc/testsuite/gcc.target/i386/pr71346.c > new file mode 100644 > index 0000000..0a15869 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/i386/pr71346.c > @@ -0,0 +1,25 @@ > +/* PR target/71346 */ > +/* { dg-do compile { target { ! ia32 } } } */ > +/* { dg-options "-O2 -ftree-vectorize -ffast-math -march=knl" } */ > + > +typedef int rvec[3]; > +int a; > +float b, c, d, g; > +rvec *e, *f; > +void fn2(float h, float g); > + > +void > +fn1() > +{ > + float h; > + for (; a; a++) { > + h += e[a][0] * f[a][0]; > + b += e[a][0] * f[a][1]; > + c += e[a][2] * f[a][0]; > + d += e[a][2] * f[a][1]; > + g += e[a][2] * f[a][2]; > + } > + fn2(h, g); > +} > + > +/* { dg-final { scan-assembler-not "vshufps\[ \\t\]+\[^\n\]*%\xmm(?:1\[6-9\]|\[2-3\]\[0-9\])" } } */ Jakub
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index b348f2d..1267897 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -6837,7 +6837,7 @@ "operands[1] = gen_lowpart (SFmode, operands[1]);") (define_insn_and_split "*sse4_1_extractps" - [(set (match_operand:SF 0 "nonimmediate_operand" "=rm,rm,rm,v,v") + [(set (match_operand:SF 0 "nonimmediate_operand" "=rm,rm,rm,Yv,Yv") (vec_select:SF (match_operand:V4SF 1 "register_operand" "Yr,*x,v,0,v") (parallel [(match_operand:SI 2 "const_0_to_3_operand" "n,n,n,n,n")])))] diff --git a/gcc/testsuite/gcc.target/i386/pr71346.c b/gcc/testsuite/gcc.target/i386/pr71346.c new file mode 100644 index 0000000..0a15869 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr71346.c @@ -0,0 +1,25 @@ +/* PR target/71346 */ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -ftree-vectorize -ffast-math -march=knl" } */ + +typedef int rvec[3]; +int a; +float b, c, d, g; +rvec *e, *f; +void fn2(float h, float g); + +void +fn1() +{ + float h; + for (; a; a++) { + h += e[a][0] * f[a][0]; + b += e[a][0] * f[a][1]; + c += e[a][2] * f[a][0]; + d += e[a][2] * f[a][1]; + g += e[a][2] * f[a][2]; + } + fn2(h, g); +} + +/* { dg-final { scan-assembler-not "vshufps\[ \\t\]+\[^\n\]*%\xmm(?:1\[6-9\]|\[2-3\]\[0-9\])" } } */
Hello, Patch limits constraint for scalar operand in split to AVX-512VL. Boostrap/regtest in progress for x86_64/ia32. I'll check it in if pass. PR target/71346. gcc/ * config/i386/sse.md (define_insn_and_split "*vec_extractv4sf_0"): Use `Yv' for scalar operand. testsuite/ * gcc.target/i386/prr71346.c: New test. -- Thanks, K commit 6c0021bea7a5be8d9a10ef3f2fb30c1228f53d48 Author: Kirill Yukhin <kirill.yukhin@intel.com> Date: Mon May 30 16:31:28 2016 +0300 AVX-512. Fix PR target/71346.