--- gcc/config/i386/sse.md.jj	2016-05-09 11:38:36.000000000 +0200
+++ gcc/config/i386/sse.md	2016-05-09 12:34:58.839865460 +0200
@@ -11500,54 +11500,57 @@ (define_expand "vec_pack_trunc_<mode>"
 })
 
 (define_insn "<sse2_avx2>_packsswb<mask_name>"
-  [(set (match_operand:VI1_AVX512 0 "register_operand" "=x,x")
+  [(set (match_operand:VI1_AVX512 0 "register_operand" "=x,x,v")
 	(vec_concat:VI1_AVX512
 	  (ss_truncate:<ssehalfvecmode>
-	    (match_operand:<sseunpackmode> 1 "register_operand" "0,v"))
+	    (match_operand:<sseunpackmode> 1 "register_operand" "0,x,v"))
 	  (ss_truncate:<ssehalfvecmode>
-	    (match_operand:<sseunpackmode> 2 "vector_operand" "xBm,vm"))))]
+	    (match_operand:<sseunpackmode> 2 "vector_operand" "xBm,xm,vm"))))]
   "TARGET_SSE2 && <mask_mode512bit_condition> && <mask_avx512bw_condition>"
   "@
    packsswb\t{%2, %0|%0, %2}
+   vpacksswb\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}
    vpacksswb\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
-  [(set_attr "isa" "noavx,avx")
+  [(set_attr "isa" "noavx,avx,avx512bw")
    (set_attr "type" "sselog")
-   (set_attr "prefix_data16" "1,*")
-   (set_attr "prefix" "orig,maybe_evex")
+   (set_attr "prefix_data16" "1,*,*")
+   (set_attr "prefix" "orig,<mask_prefix>,evex")
    (set_attr "mode" "<sseinsnmode>")])
 
 (define_insn "<sse2_avx2>_packssdw<mask_name>"
-  [(set (match_operand:VI2_AVX2 0 "register_operand" "=x,v")
+  [(set (match_operand:VI2_AVX2 0 "register_operand" "=x,x,v")
 	(vec_concat:VI2_AVX2
 	  (ss_truncate:<ssehalfvecmode>
-	    (match_operand:<sseunpackmode> 1 "register_operand" "0,v"))
+	    (match_operand:<sseunpackmode> 1 "register_operand" "0,x,v"))
 	  (ss_truncate:<ssehalfvecmode>
-	    (match_operand:<sseunpackmode> 2 "vector_operand" "xBm,vm"))))]
+	    (match_operand:<sseunpackmode> 2 "vector_operand" "xBm,xm,vm"))))]
   "TARGET_SSE2 && <mask_mode512bit_condition> && <mask_avx512bw_condition>"
   "@
    packssdw\t{%2, %0|%0, %2}
+   vpackssdw\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}
    vpackssdw\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
-  [(set_attr "isa" "noavx,avx")
+  [(set_attr "isa" "noavx,avx,avx512bw")
    (set_attr "type" "sselog")
-   (set_attr "prefix_data16" "1,*")
-   (set_attr "prefix" "orig,vex")
+   (set_attr "prefix_data16" "1,*,*")
+   (set_attr "prefix" "orig,<mask_prefix>,evex")
    (set_attr "mode" "<sseinsnmode>")])
 
 (define_insn "<sse2_avx2>_packuswb<mask_name>"
-  [(set (match_operand:VI1_AVX512 0 "register_operand" "=x,x")
+  [(set (match_operand:VI1_AVX512 0 "register_operand" "=x,x,v")
 	(vec_concat:VI1_AVX512
 	  (us_truncate:<ssehalfvecmode>
-	    (match_operand:<sseunpackmode> 1 "register_operand" "0,v"))
+	    (match_operand:<sseunpackmode> 1 "register_operand" "0,x,v"))
 	  (us_truncate:<ssehalfvecmode>
-	    (match_operand:<sseunpackmode> 2 "vector_operand" "xBm,vm"))))]
+	    (match_operand:<sseunpackmode> 2 "vector_operand" "xBm,xm,vm"))))]
   "TARGET_SSE2 && <mask_mode512bit_condition> && <mask_avx512bw_condition>"
   "@
    packuswb\t{%2, %0|%0, %2}
+   vpackuswb\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}
    vpackuswb\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
-  [(set_attr "isa" "noavx,avx")
+  [(set_attr "isa" "noavx,avx,avx512bw")
    (set_attr "type" "sselog")
-   (set_attr "prefix_data16" "1,*")
-   (set_attr "prefix" "orig,vex")
+   (set_attr "prefix_data16" "1,*,*")
+   (set_attr "prefix" "orig,<mask_prefix>,evex")
    (set_attr "mode" "<sseinsnmode>")])
 
 (define_insn "avx512bw_interleave_highv64qi<mask_name>"
@@ -14572,21 +14575,22 @@ (define_insn "<sse4_1_avx2>_mpsadbw"
    (set_attr "mode" "<sseinsnmode>")])
 
 (define_insn "<sse4_1_avx2>_packusdw<mask_name>"
-  [(set (match_operand:VI2_AVX2 0 "register_operand" "=Yr,*x,v")
+  [(set (match_operand:VI2_AVX2 0 "register_operand" "=Yr,*x,x,v")
 	(vec_concat:VI2_AVX2
 	  (us_truncate:<ssehalfvecmode>
-	    (match_operand:<sseunpackmode> 1 "register_operand" "0,0,v"))
+	    (match_operand:<sseunpackmode> 1 "register_operand" "0,0,x,v"))
 	  (us_truncate:<ssehalfvecmode>
-	    (match_operand:<sseunpackmode> 2 "vector_operand" "YrBm,*xBm,vm"))))]
+	    (match_operand:<sseunpackmode> 2 "vector_operand" "YrBm,*xBm,xm,vm"))))]
   "TARGET_SSE4_1 && <mask_mode512bit_condition> && <mask_avx512bw_condition>"
   "@
    packusdw\t{%2, %0|%0, %2}
    packusdw\t{%2, %0|%0, %2}
+   vpackusdw\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}
    vpackusdw\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
-  [(set_attr "isa" "noavx,noavx,avx")
+  [(set_attr "isa" "noavx,noavx,avx,avx512bw")
    (set_attr "type" "sselog")
    (set_attr "prefix_extra" "1")
-   (set_attr "prefix" "orig,orig,maybe_evex")
+   (set_attr "prefix" "orig,orig,<mask_prefix>,evex")
    (set_attr "mode" "<sseinsnmode>")])
 
 (define_insn "<sse4_1_avx2>_pblendvb"
--- gcc/testsuite/gcc.target/i386/avx512vl-pack-1.c.jj	2016-05-09 12:16:52.062562903 +0200
+++ gcc/testsuite/gcc.target/i386/avx512vl-pack-1.c	2016-05-09 12:21:42.786628535 +0200
@@ -0,0 +1,68 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx512vl -mno-avx512bw" } */
+
+#include <x86intrin.h>
+
+__m128i
+f1 (__m128i a, __m128i b)
+{
+  return _mm_packs_epi16 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "vpacksswb\[^\n\r\]*xmm\[0-9\]" 1 } } */
+
+__m128i
+f2 (__m128i a, __m128i b)
+{
+  return _mm_packs_epi32 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "vpackssdw\[^\n\r\]*xmm\[0-9\]" 1 } } */
+
+__m128i
+f3 (__m128i a, __m128i b)
+{
+  return _mm_packus_epi16 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "vpackuswb\[^\n\r\]*xmm\[0-9\]" 1 } } */
+
+__m128i
+f4 (__m128i a, __m128i b)
+{
+  return _mm_packus_epi32 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "vpackusdw\[^\n\r\]*xmm\[0-9\]" 1 } } */
+
+__m256i
+f5 (__m256i a, __m256i b)
+{
+  return _mm256_packs_epi16 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "vpacksswb\[^\n\r\]*ymm\[0-9\]" 1 } } */
+
+__m256i
+f6 (__m256i a, __m256i b)
+{
+  return _mm256_packs_epi32 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "vpackssdw\[^\n\r\]*ymm\[0-9\]" 1 } } */
+
+__m256i
+f7 (__m256i a, __m256i b)
+{
+  return _mm256_packus_epi16 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "vpackuswb\[^\n\r\]*ymm\[0-9\]" 1 } } */
+
+__m256i
+f8 (__m256i a, __m256i b)
+{
+  return _mm256_packus_epi32 (a, b);
+}
+
+/* { dg-final { scan-assembler-times "vpackusdw\[^\n\r\]*ymm\[0-9\]" 1 } } */
--- gcc/testsuite/gcc.target/i386/avx512vl-pack-2.c.jj	2016-05-09 12:16:54.961523671 +0200
+++ gcc/testsuite/gcc.target/i386/avx512vl-pack-2.c	2016-05-09 12:24:13.532588490 +0200
@@ -0,0 +1,108 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -mavx512vl -mno-avx512bw" } */
+
+#include <x86intrin.h>
+
+__m128i
+f1 (__m128i a, __m128i b)
+{
+  register __m128i c __asm ("xmm16") = a;
+  asm volatile ("" : "+v" (c));
+  c = _mm_packs_epi16 (c, b);
+  asm volatile ("" : "+v" (c));
+  return c;
+}
+
+/* { dg-final { scan-assembler-times "vpacksswb\[^\n\r\]*xmm\[0-9\]" 1 } } */
+/* { dg-final { scan-assembler-not "vpacksswb\[^\n\r\]*xmm16" } } */
+
+__m128i
+f2 (__m128i a, __m128i b)
+{
+  register __m128i c __asm ("xmm16") = a;
+  asm volatile ("" : "+v" (c));
+  c = _mm_packs_epi32 (c, b);
+  asm volatile ("" : "+v" (c));
+  return c;
+}
+
+/* { dg-final { scan-assembler-times "vpackssdw\[^\n\r\]*xmm\[0-9\]" 1 } } */
+/* { dg-final { scan-assembler-not "vpackssdw\[^\n\r\]*xmm16" } } */
+
+__m128i
+f3 (__m128i a, __m128i b)
+{
+  register __m128i c __asm ("xmm16") = a;
+  asm volatile ("" : "+v" (c));
+  c = _mm_packus_epi16 (c, b);
+  asm volatile ("" : "+v" (c));
+  return c;
+}
+
+/* { dg-final { scan-assembler-times "vpackuswb\[^\n\r\]*xmm\[0-9\]" 1 } } */
+/* { dg-final { scan-assembler-not "vpackuswb\[^\n\r\]*xmm16" } } */
+
+__m128i
+f4 (__m128i a, __m128i b)
+{
+  register __m128i c __asm ("xmm16") = a;
+  asm volatile ("" : "+v" (c));
+  c = _mm_packus_epi32 (c, b);
+  asm volatile ("" : "+v" (c));
+  return c;
+}
+
+/* { dg-final { scan-assembler-times "vpackusdw\[^\n\r\]*xmm\[0-9\]" 1 } } */
+/* { dg-final { scan-assembler-not "vpackusdw\[^\n\r\]*xmm16" } } */
+
+__m256i
+f5 (__m256i a, __m256i b)
+{
+  register __m256i c __asm ("xmm16") = a;
+  asm volatile ("" : "+v" (c));
+  c = _mm256_packs_epi16 (c, b);
+  asm volatile ("" : "+v" (c));
+  return c;
+}
+
+/* { dg-final { scan-assembler-times "vpacksswb\[^\n\r\]*ymm\[0-9\]" 1 } } */
+/* { dg-final { scan-assembler-not "vpacksswb\[^\n\r\]*ymm16" } } */
+
+__m256i
+f6 (__m256i a, __m256i b)
+{
+  register __m256i c __asm ("xmm16") = a;
+  asm volatile ("" : "+v" (c));
+  c = _mm256_packs_epi32 (c, b);
+  asm volatile ("" : "+v" (c));
+  return c;
+}
+
+/* { dg-final { scan-assembler-times "vpackssdw\[^\n\r\]*ymm\[0-9\]" 1 } } */
+/* { dg-final { scan-assembler-not "vpackssdw\[^\n\r\]*ymm16" } } */
+
+__m256i
+f7 (__m256i a, __m256i b)
+{
+  register __m256i c __asm ("xmm16") = a;
+  asm volatile ("" : "+v" (c));
+  c = _mm256_packus_epi16 (c, b);
+  asm volatile ("" : "+v" (c));
+  return c;
+}
+
+/* { dg-final { scan-assembler-times "vpackuswb\[^\n\r\]*ymm\[0-9\]" 1 } } */
+/* { dg-final { scan-assembler-not "vpackuswb\[^\n\r\]*ymm16" } } */
+
+__m256i
+f8 (__m256i a, __m256i b)
+{
+  register __m256i c __asm ("xmm16") = a;
+  asm volatile ("" : "+v" (c));
+  c = _mm256_packus_epi32 (c, b);
+  asm volatile ("" : "+v" (c));
+  return c;
+}
+
+/* { dg-final { scan-assembler-times "vpackusdw\[^\n\r\]*ymm\[0-9\]" 1 } } */
+/* { dg-final { scan-assembler-not "vpackusdw\[^\n\r\]*ymm16" } } */
--- gcc/testsuite/gcc.target/i386/avx512bw-pack-2.c.jj	2016-05-09 12:28:02.869486414 +0200
+++ gcc/testsuite/gcc.target/i386/avx512bw-pack-2.c	2016-05-09 12:29:06.941620616 +0200
@@ -0,0 +1,100 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -mavx512vl -mavx512bw" } */
+
+#include <x86intrin.h>
+
+__m128i
+f1 (__m128i a, __m128i b)
+{
+  register __m128i c __asm ("xmm16") = a;
+  asm volatile ("" : "+v" (c));
+  c = _mm_packs_epi16 (c, b);
+  asm volatile ("" : "+v" (c));
+  return c;
+}
+
+/* { dg-final { scan-assembler-times "vpacksswb\[^\n\r\]*xmm16" 1 } } */
+
+__m128i
+f2 (__m128i a, __m128i b)
+{
+  register __m128i c __asm ("xmm16") = a;
+  asm volatile ("" : "+v" (c));
+  c = _mm_packs_epi32 (c, b);
+  asm volatile ("" : "+v" (c));
+  return c;
+}
+
+/* { dg-final { scan-assembler-times "vpackssdw\[^\n\r\]*xmm16" 1 } } */
+
+__m128i
+f3 (__m128i a, __m128i b)
+{
+  register __m128i c __asm ("xmm16") = a;
+  asm volatile ("" : "+v" (c));
+  c = _mm_packus_epi16 (c, b);
+  asm volatile ("" : "+v" (c));
+  return c;
+}
+
+/* { dg-final { scan-assembler-times "vpackuswb\[^\n\r\]*xmm16" 1 } } */
+
+__m128i
+f4 (__m128i a, __m128i b)
+{
+  register __m128i c __asm ("xmm16") = a;
+  asm volatile ("" : "+v" (c));
+  c = _mm_packus_epi32 (c, b);
+  asm volatile ("" : "+v" (c));
+  return c;
+}
+
+/* { dg-final { scan-assembler-times "vpackusdw\[^\n\r\]*xmm16" 1 } } */
+
+__m256i
+f5 (__m256i a, __m256i b)
+{
+  register __m256i c __asm ("xmm16") = a;
+  asm volatile ("" : "+v" (c));
+  c = _mm256_packs_epi16 (c, b);
+  asm volatile ("" : "+v" (c));
+  return c;
+}
+
+/* { dg-final { scan-assembler-times "vpacksswb\[^\n\r\]*ymm16" 1 } } */
+
+__m256i
+f6 (__m256i a, __m256i b)
+{
+  register __m256i c __asm ("xmm16") = a;
+  asm volatile ("" : "+v" (c));
+  c = _mm256_packs_epi32 (c, b);
+  asm volatile ("" : "+v" (c));
+  return c;
+}
+
+/* { dg-final { scan-assembler-times "vpackssdw\[^\n\r\]*ymm16" 1 } } */
+
+__m256i
+f7 (__m256i a, __m256i b)
+{
+  register __m256i c __asm ("xmm16") = a;
+  asm volatile ("" : "+v" (c));
+  c = _mm256_packus_epi16 (c, b);
+  asm volatile ("" : "+v" (c));
+  return c;
+}
+
+/* { dg-final { scan-assembler-times "vpackuswb\[^\n\r\]*ymm16" 1 } } */
+
+__m256i
+f8 (__m256i a, __m256i b)
+{
+  register __m256i c __asm ("xmm16") = a;
+  asm volatile ("" : "+v" (c));
+  c = _mm256_packus_epi32 (c, b);
+  asm volatile ("" : "+v" (c));
+  return c;
+}
+
+/* { dg-final { scan-assembler-times "vpackusdw\[^\n\r\]*ymm16" 1 } } */
