From patchwork Wed May 4 19:43:02 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jakub Jelinek X-Patchwork-Id: 618601 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3r0T410tgDz9t3r for ; Thu, 5 May 2016 05:43:28 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=ehC4hGpN; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:message-id:reply-to:mime-version :content-type; q=dns; s=default; b=pFRWIrQPAUwPy2cYZTl0mozfqpm/8 891UCn8LhaFW2oIY3GkTDDruufhMq5ZsaGsWk/PmbFFXLmVLL3baDObth5ZzLivk CfM6wAZnkiniOmyHvmmtF919be7uAlljGa/393nNnR1pTh72H4OGc9w/SBZu3QpN UnIbnUk6ayRnGs= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:message-id:reply-to:mime-version :content-type; s=default; bh=0w1AW/uh9gFJzo9YOf0TavFK01Y=; b=ehC 4hGpNSh8S+P6MLndV07ZdfDeeZyRPGCwL/5iiLwTxkLtoqIL4Cf0MH/S+DXHlrL7 dLgwUHFtEZ3pBHmZKt5Xmz2U+AOwGkBU2exIi7Dy+yuX0Iko6QHCINDJCJdcntyv arw1O1QFPnZWE42fChYVRTyHh66IbmleqvX4MAjY= Received: (qmail 90353 invoked by alias); 4 May 2016 19:43:22 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 90344 invoked by uid 89); 4 May 2016 19:43:21 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-4.0 required=5.0 tests=BAYES_00, RP_MATCHES_RCVD, SPF_HELO_PASS autolearn=ham version=3.3.2 spammy=mas, i386.c, i386c, UD:i386.c X-HELO: mx1.redhat.com Received: from mx1.redhat.com (HELO mx1.redhat.com) (209.132.183.28) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-GCM-SHA384 encrypted) ESMTPS; Wed, 04 May 2016 19:43:08 +0000 Received: from int-mx11.intmail.prod.int.phx2.redhat.com (int-mx11.intmail.prod.int.phx2.redhat.com [10.5.11.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id D83DA6266E; Wed, 4 May 2016 19:43:06 +0000 (UTC) Received: from tucnak.zalov.cz (ovpn-113-135.phx2.redhat.com [10.3.113.135]) by int-mx11.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id u44Jh5JH008426 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Wed, 4 May 2016 15:43:06 -0400 Received: from tucnak.zalov.cz (localhost [127.0.0.1]) by tucnak.zalov.cz (8.15.2/8.15.2) with ESMTP id u44Jh3tM013659; Wed, 4 May 2016 21:43:03 +0200 Received: (from jakub@localhost) by tucnak.zalov.cz (8.15.2/8.15.2/Submit) id u44Jh2k2013653; Wed, 4 May 2016 21:43:02 +0200 Date: Wed, 4 May 2016 21:43:02 +0200 From: Jakub Jelinek To: Uros Bizjak , Kirill Yukhin Cc: gcc-patches@gcc.gnu.org Subject: [PATCH] Improve other 13 define_insns Message-ID: <20160504194302.GO26501@tucnak.zalov.cz> Reply-To: Jakub Jelinek MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.5.24 (2015-08-30) X-IsSubscribed: yes Hi! This patch tweaks more define_insns at once, again all the insns should be already in AVX512F or AVX512VL. Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk? 2016-05-04 Jakub Jelinek * config/i386/sse.md (sse_shufps_, sse_storehps, sse_loadhps, sse_storelps, sse_movss, avx2_vec_dup, avx2_vec_dupv8sf_1, sse2_shufpd_, sse2_storehpd, sse2_storelpd, sse2_loadhpd, sse2_loadlpd, sse2_movsd): Use v instead of x in vex or maybe_vex alternatives, use maybe_evex instead of vex in prefix. Jakub --- gcc/config/i386/sse.md.jj 2016-05-04 14:36:08.000000000 +0200 +++ gcc/config/i386/sse.md 2016-05-04 15:16:44.180894303 +0200 @@ -6219,11 +6219,11 @@ (define_insn "sse_shufps_v4sf_mask" (set_attr "mode" "V4SF")]) (define_insn "sse_shufps_" - [(set (match_operand:VI4F_128 0 "register_operand" "=x,x") + [(set (match_operand:VI4F_128 0 "register_operand" "=x,v") (vec_select:VI4F_128 (vec_concat: - (match_operand:VI4F_128 1 "register_operand" "0,x") - (match_operand:VI4F_128 2 "vector_operand" "xBm,xm")) + (match_operand:VI4F_128 1 "register_operand" "0,v") + (match_operand:VI4F_128 2 "vector_operand" "xBm,vm")) (parallel [(match_operand 3 "const_0_to_3_operand") (match_operand 4 "const_0_to_3_operand") (match_operand 5 "const_4_to_7_operand") @@ -6250,13 +6250,13 @@ (define_insn "sse_shufps_" [(set_attr "isa" "noavx,avx") (set_attr "type" "sseshuf") (set_attr "length_immediate" "1") - (set_attr "prefix" "orig,vex") + (set_attr "prefix" "orig,maybe_evex") (set_attr "mode" "V4SF")]) (define_insn "sse_storehps" - [(set (match_operand:V2SF 0 "nonimmediate_operand" "=m,x,x") + [(set (match_operand:V2SF 0 "nonimmediate_operand" "=m,v,v") (vec_select:V2SF - (match_operand:V4SF 1 "nonimmediate_operand" "x,x,o") + (match_operand:V4SF 1 "nonimmediate_operand" "v,v,o") (parallel [(const_int 2) (const_int 3)])))] "TARGET_SSE" "@ @@ -6288,12 +6288,12 @@ (define_expand "sse_loadhps_exp" }) (define_insn "sse_loadhps" - [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,x,x,x,o") + [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,v,x,v,o") (vec_concat:V4SF (vec_select:V2SF - (match_operand:V4SF 1 "nonimmediate_operand" " 0,x,0,x,0") + (match_operand:V4SF 1 "nonimmediate_operand" " 0,v,0,v,0") (parallel [(const_int 0) (const_int 1)])) - (match_operand:V2SF 2 "nonimmediate_operand" " m,m,x,x,x")))] + (match_operand:V2SF 2 "nonimmediate_operand" " m,m,x,v,v")))] "TARGET_SSE" "@ movhps\t{%2, %0|%0, %q2} @@ -6303,13 +6303,13 @@ (define_insn "sse_loadhps" %vmovlps\t{%2, %H0|%H0, %2}" [(set_attr "isa" "noavx,avx,noavx,avx,*") (set_attr "type" "ssemov") - (set_attr "prefix" "orig,vex,orig,vex,maybe_vex") + (set_attr "prefix" "orig,maybe_evex,orig,maybe_evex,maybe_vex") (set_attr "mode" "V2SF,V2SF,V4SF,V4SF,V2SF")]) (define_insn "sse_storelps" - [(set (match_operand:V2SF 0 "nonimmediate_operand" "=m,x,x") + [(set (match_operand:V2SF 0 "nonimmediate_operand" "=m,v,v") (vec_select:V2SF - (match_operand:V4SF 1 "nonimmediate_operand" " x,x,m") + (match_operand:V4SF 1 "nonimmediate_operand" " v,v,m") (parallel [(const_int 0) (const_int 1)])))] "TARGET_SSE" "@ @@ -6341,11 +6341,11 @@ (define_expand "sse_loadlps_exp" }) (define_insn "sse_loadlps" - [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,x,x,x,m") + [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,v,x,v,m") (vec_concat:V4SF - (match_operand:V2SF 2 "nonimmediate_operand" " 0,x,m,m,x") + (match_operand:V2SF 2 "nonimmediate_operand" " 0,v,m,m,v") (vec_select:V2SF - (match_operand:V4SF 1 "nonimmediate_operand" " x,x,0,x,0") + (match_operand:V4SF 1 "nonimmediate_operand" " x,v,0,v,0") (parallel [(const_int 2) (const_int 3)]))))] "TARGET_SSE" "@ @@ -6357,14 +6357,14 @@ (define_insn "sse_loadlps" [(set_attr "isa" "noavx,avx,noavx,avx,*") (set_attr "type" "sseshuf,sseshuf,ssemov,ssemov,ssemov") (set_attr "length_immediate" "1,1,*,*,*") - (set_attr "prefix" "orig,vex,orig,vex,maybe_vex") + (set_attr "prefix" "orig,maybe_evex,orig,maybe_evex,maybe_vex") (set_attr "mode" "V4SF,V4SF,V2SF,V2SF,V2SF")]) (define_insn "sse_movss" - [(set (match_operand:V4SF 0 "register_operand" "=x,x") + [(set (match_operand:V4SF 0 "register_operand" "=x,v") (vec_merge:V4SF - (match_operand:V4SF 2 "register_operand" " x,x") - (match_operand:V4SF 1 "register_operand" " 0,x") + (match_operand:V4SF 2 "register_operand" " x,v") + (match_operand:V4SF 1 "register_operand" " 0,v") (const_int 1)))] "TARGET_SSE" "@ @@ -6372,31 +6372,31 @@ (define_insn "sse_movss" vmovss\t{%2, %1, %0|%0, %1, %2}" [(set_attr "isa" "noavx,avx") (set_attr "type" "ssemov") - (set_attr "prefix" "orig,vex") + (set_attr "prefix" "orig,maybe_evex") (set_attr "mode" "SF")]) (define_insn "avx2_vec_dup" - [(set (match_operand:VF1_128_256 0 "register_operand" "=x") + [(set (match_operand:VF1_128_256 0 "register_operand" "=v") (vec_duplicate:VF1_128_256 (vec_select:SF - (match_operand:V4SF 1 "register_operand" "x") + (match_operand:V4SF 1 "register_operand" "v") (parallel [(const_int 0)]))))] "TARGET_AVX2" "vbroadcastss\t{%1, %0|%0, %1}" [(set_attr "type" "sselog1") - (set_attr "prefix" "vex") + (set_attr "prefix" "maybe_evex") (set_attr "mode" "")]) (define_insn "avx2_vec_dupv8sf_1" - [(set (match_operand:V8SF 0 "register_operand" "=x") + [(set (match_operand:V8SF 0 "register_operand" "=v") (vec_duplicate:V8SF (vec_select:SF - (match_operand:V8SF 1 "register_operand" "x") + (match_operand:V8SF 1 "register_operand" "v") (parallel [(const_int 0)]))))] "TARGET_AVX2" "vbroadcastss\t{%x1, %0|%0, %x1}" [(set_attr "type" "sselog1") - (set_attr "prefix" "vex") + (set_attr "prefix" "maybe_evex") (set_attr "mode" "V8SF")]) (define_insn "avx512f_vec_dup_1" @@ -8248,11 +8262,11 @@ (define_insn "vec_interleave_lowv2di" - [(set (match_operand:VI8F_128 0 "register_operand" "=x,x") + [(set (match_operand:VI8F_128 0 "register_operand" "=x,v") (vec_select:VI8F_128 (vec_concat: - (match_operand:VI8F_128 1 "register_operand" "0,x") - (match_operand:VI8F_128 2 "vector_operand" "xBm,xm")) + (match_operand:VI8F_128 1 "register_operand" "0,v") + (match_operand:VI8F_128 2 "vector_operand" "xBm,vm")) (parallel [(match_operand 3 "const_0_to_1_operand") (match_operand 4 "const_2_to_3_operand")])))] "TARGET_SSE2" @@ -8275,15 +8289,15 @@ (define_insn "sse2_shufpd_" [(set_attr "isa" "noavx,avx") (set_attr "type" "sseshuf") (set_attr "length_immediate" "1") - (set_attr "prefix" "orig,vex") + (set_attr "prefix" "orig,maybe_evex") (set_attr "mode" "V2DF")]) ;; Avoid combining registers from different units in a single alternative, ;; see comment above inline_secondary_memory_needed function in i386.c (define_insn "sse2_storehpd" - [(set (match_operand:DF 0 "nonimmediate_operand" "=m,x,x,x,*f,r") + [(set (match_operand:DF 0 "nonimmediate_operand" "=m,x,v,x,*f,r") (vec_select:DF - (match_operand:V2DF 1 "nonimmediate_operand" " x,0,x,o,o,o") + (match_operand:V2DF 1 "nonimmediate_operand" " v,0,v,o,o,o") (parallel [(const_int 1)])))] "TARGET_SSE2 && !(MEM_P (operands[0]) && MEM_P (operands[1]))" "@ @@ -8301,7 +8315,7 @@ (define_insn "sse2_storehpd" (not (match_test "TARGET_AVX"))) (const_string "1") (const_string "*"))) - (set_attr "prefix" "maybe_vex,orig,vex,*,*,*") + (set_attr "prefix" "maybe_vex,orig,maybe_evex,*,*,*") (set_attr "mode" "V1DF,V1DF,V2DF,DF,DF,DF")]) (define_split @@ -8346,7 +8346,7 @@ (define_insn "sse2_storelpd" [(set (match_operand:DF 0 "nonimmediate_operand" "=m,x,x,*f,r") (vec_select:DF - (match_operand:V2DF 1 "nonimmediate_operand" " x,x,m,m,m") + (match_operand:V2DF 1 "nonimmediate_operand" " v,x,m,m,m") (parallel [(const_int 0)])))] "TARGET_SSE2 && !(MEM_P (operands[0]) && MEM_P (operands[1]))" "@ @@ -8393,14 +8407,14 @@ (define_expand "sse2_loadhpd_exp" ;; see comment above inline_secondary_memory_needed function in i386.c (define_insn "sse2_loadhpd" [(set (match_operand:V2DF 0 "nonimmediate_operand" - "=x,x,x,x,o,o ,o") + "=x,v,x,v,o,o ,o") (vec_concat:V2DF (vec_select:DF (match_operand:V2DF 1 "nonimmediate_operand" - " 0,x,0,x,0,0 ,0") + " 0,v,0,v,0,0 ,0") (parallel [(const_int 0)])) (match_operand:DF 2 "nonimmediate_operand" - " m,m,x,x,x,*f,r")))] + " m,m,x,v,x,*f,r")))] "TARGET_SSE2 && !(MEM_P (operands[1]) && MEM_P (operands[2]))" "@ movhpd\t{%2, %0|%0, %2} @@ -8413,7 +8427,7 @@ (define_insn "sse2_loadhpd" [(set_attr "isa" "noavx,avx,noavx,avx,*,*,*") (set_attr "type" "ssemov,ssemov,sselog,sselog,ssemov,fmov,imov") (set_attr "prefix_data16" "1,*,*,*,*,*,*") - (set_attr "prefix" "orig,vex,orig,vex,*,*,*") + (set_attr "prefix" "orig,maybe_evex,orig,maybe_evex,*,*,*") (set_attr "mode" "V1DF,V1DF,V2DF,V2DF,DF,DF,DF")]) (define_split @@ -8449,13 +8463,13 @@ (define_expand "sse2_loadlpd_exp" ;; see comment above inline_secondary_memory_needed function in i386.c (define_insn "sse2_loadlpd" [(set (match_operand:V2DF 0 "nonimmediate_operand" - "=x,x,x,x,x,x,x,x,m,m ,m") + "=v,x,v,x,v,x,x,v,m,m ,m") (vec_concat:V2DF (match_operand:DF 2 "nonimmediate_operand" - "xm,m,m,x,x,0,0,x,x,*f,r") + "vm,m,m,x,v,0,0,v,x,*f,r") (vec_select:DF (match_operand:V2DF 1 "vector_move_operand" - " C,0,x,0,x,x,o,o,0,0 ,0") + " C,0,v,0,v,x,o,o,0,0 ,0") (parallel [(const_int 1)]))))] "TARGET_SSE2 && !(MEM_P (operands[1]) && MEM_P (operands[2]))" "@ @@ -8482,7 +8496,7 @@ (define_insn "sse2_loadlpd" (const_string "ssemov"))) (set_attr "prefix_data16" "*,1,*,*,*,*,1,*,*,*,*") (set_attr "length_immediate" "*,*,*,*,*,1,*,*,*,*,*") - (set_attr "prefix" "maybe_vex,orig,vex,orig,vex,orig,orig,vex,*,*,*") + (set_attr "prefix" "maybe_vex,orig,maybe_evex,orig,maybe_evex,orig,orig,maybe_evex,*,*,*") (set_attr "mode" "DF,V1DF,V1DF,V1DF,V1DF,V2DF,V1DF,V1DF,DF,DF,DF")]) (define_split @@ -8495,10 +8509,10 @@ (define_split "operands[0] = adjust_address (operands[0], DFmode, 0);") (define_insn "sse2_movsd" - [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,x,x,m,x,x,x,o") + [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,v,x,v,m,x,x,v,o") (vec_merge:V2DF - (match_operand:V2DF 2 "nonimmediate_operand" " x,x,m,m,x,0,0,x,0") - (match_operand:V2DF 1 "nonimmediate_operand" " 0,x,0,x,0,x,o,o,x") + (match_operand:V2DF 2 "nonimmediate_operand" " x,v,m,m,v,0,0,v,0") + (match_operand:V2DF 1 "nonimmediate_operand" " 0,v,0,v,0,x,o,o,v") (const_int 1)))] "TARGET_SSE2" "@ @@ -8524,7 +8538,7 @@ (define_insn "sse2_movsd" (const_string "1") (const_string "*"))) (set_attr "length_immediate" "*,*,*,*,*,1,*,*,*") - (set_attr "prefix" "orig,vex,orig,vex,maybe_vex,orig,orig,vex,maybe_vex") + (set_attr "prefix" "orig,maybe_evex,orig,maybe_evex,maybe_vex,orig,orig,maybe_evex,maybe_vex") (set_attr "mode" "DF,DF,V1DF,V1DF,V1DF,V2DF,V1DF,V1DF,V1DF")]) (define_insn "vec_dupv2df"