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Don't emit AVX512DQ insns for -mavx512vl -mno-avx512dq (PR target/70927)

Message ID 20160503182328.GF26501@tucnak.zalov.cz
State New
Headers show

Commit Message

Jakub Jelinek May 3, 2016, 6:23 p.m. UTC 
Hi!

While working on a patch I'm going to post momentarily, I've noticed that
we sometimes emit AVX512DQ specific instructions even when avx512dq is not
enabled (in particular, EVEX andnps and andnpd are AVX512DQ plus if
they have 128-bit or 256-bit arguments, also AVX512VL).

I'm not 100% happy about the patch, because (pre-existing issue)
get_attr_mode doesn't reflect that the insn is in that not a vector float
insn, but perhaps we'd need to use another alternative and some ugly
conditionals in mode attribute for that case.

Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk and
after a while 6.2, or do you prefer some other fix?

2016-05-03  Jakub Jelinek  <jakub@redhat.com>

	PR target/70927
	* config/i386/sse.md (<sse>_andnot<mode>3<mask_name>),
	*<code><mode>3<mask_name>): For !TARGET_AVX512DQ, use vp*[dq]
	instead of v*p[sd] instructions even if !<mask_applied> and
	128-bit/256-bit vectors, if any operand is EXT_REX_SSE_REG_P.


	Jakub
diff mbox

Patch

--- gcc/config/i386/sse.md.jj	2016-05-03 13:34:09.946986488 +0200
+++ gcc/config/i386/sse.md	2016-05-03 17:38:02.486935094 +0200
@@ -2817,7 +2817,11 @@  (define_insn "<sse>_andnot<mode>3<mask_n
     }
 
   /* There is no vandnp[sd] in avx512f.  Use vpandn[qd].  */
-  if (<mask_applied> && !TARGET_AVX512DQ)
+  if (!TARGET_AVX512DQ
+      && (<mask_applied>
+	  || EXT_REX_SSE_REG_P (operands[0])
+	  || EXT_REX_SSE_REG_P (operands[1])
+	  || EXT_REX_SSE_REG_P (operands[2])))
     {
       suffix = GET_MODE_INNER (<MODE>mode) == DFmode ? "q" : "d";
       ops = "vpandn%s\t{%%2, %%1, %%0<mask_operand3_1>|%%0<mask_operand3_1>, %%1, %%2}";
@@ -2923,7 +2927,11 @@  (define_insn "*<code><mode>3<mask_name>"
     }
 
   /* There is no v<logic>p[sd] in avx512f.  Use vp<logic>[dq].  */
-  if (<mask_applied> && !TARGET_AVX512DQ)
+  if (!TARGET_AVX512DQ
+      && (<mask_applied>
+	  || EXT_REX_SSE_REG_P (operands[0])
+	  || EXT_REX_SSE_REG_P (operands[1])
+	  || EXT_REX_SSE_REG_P (operands[2])))
     {
       suffix = GET_MODE_INNER (<MODE>mode) == DFmode ? "q" : "d";
       ops = "vp<logic>%s\t{%%2, %%1, %%0<mask_operand3_1>|%%0<mask_operand3_1>, %%1, %%2}";
@@ -2961,7 +2969,12 @@  (define_insn "*<code><mode>3<mask_name>"
   ops = "";
 
   /* There is no v<logic>p[sd] in avx512f.  Use vp<logic>[dq].  */
-  if ((<MODE_SIZE> == 64 || <mask_applied>) && !TARGET_AVX512DQ)
+  if (!TARGET_AVX512DQ
+      && (<mask_applied>
+	  || <MODE_SIZE> == 64
+	  || EXT_REX_SSE_REG_P (operands[0])
+	  || EXT_REX_SSE_REG_P (operands[1])
+	  || EXT_REX_SSE_REG_P (operands[2])))
     {
       suffix = GET_MODE_INNER (<MODE>mode) == DFmode ? "q" : "d";
       ops = "p";