diff mbox

[PATCHv2,2/7] gcc/arc: Replace rI constraint with r & Cm2 for ld and update insns

Message ID 20160429115836.GH1592@embecosm.com
State New
Headers show

Commit Message

Andrew Burgess April 29, 2016, 11:58 a.m. UTC 
* Joern Wolfgang Rennecke <gnu@amylaar.uk> [2016-04-28 18:06:42 +0100]:

> On 21/04/16 12:39, Andrew Burgess wrote:
> >
> >	* config/arc/arc.md (*loadqi_update): Replace use of 'rI'
> >	constraint with separate 'r' and 'Cm2' constraints.
> >	
> Why don't you use simply rCm2 ?

You are absolutely correct.  Thank you for pointing this out.

The much simpler version of this patch is below.

Thanks,
Andrew

---

gcc/arc: Replace rI constraint with rCm2 for ld and update insns

In the load*_update instructions the constraint 'rI' was being used,
which would accept either a register or a signed 12 bit constant.  The
problem is that the 32-bit form of ld with update only takes a signed
9-bit immediate.  As such, some ld instructions could be generated that
would, when assembled be 64-bit long, however, GCC believed them to be
32-bit long.  This error in the length would cause problems during
branch shortening.

The store*_update have the same restrictions on immediate size, however,
the patterns for these instructions already only accept 9-bit
immediates, and so should be safe.

gcc/ChangeLog:

	* config/arc/arc.md (*loadqi_update): Replace use of 'rI'
	constraint with 'rCm2' constraints to limit possible immediate
	size.
	(*load_zeroextendqisi_update): Likewise.
	(*load_signextendqisi_update): Likewise.
	(*loadhi_update): Likewise.
	(*load_zeroextendhisi_update): Likewise.
	(*load_signextendhisi_update): Likewise.
	(*loadsi_update): Likewise.
	(*loadsf_update): Likewise.
---
 gcc/ChangeLog.NPS400  | 12 ++++++++++++
 gcc/config/arc/arc.md | 16 ++++++++--------
 2 files changed, 20 insertions(+), 8 deletions(-)
 create mode 100644 gcc/ChangeLog.NPS400

Comments

Joern Wolfgang Rennecke April 29, 2016, 12:08 p.m. UTC | #1 
On 29/04/16 12:58, Andrew Burgess wrote:
>
> 	* config/arc/arc.md (*loadqi_update): Replace use of 'rI'
> 	constraint with 'rCm2' constraints to limit possible immediate
> 	size.
> 	(*load_zeroextendqisi_update): Likewise.
> 	(*load_signextendqisi_update): Likewise.
> 	(*loadhi_update): Likewise.
> 	(*load_zeroextendhisi_update): Likewise.
> 	(*load_signextendhisi_update): Likewise.
> 	(*loadsi_update): Likewise.
> 	(*loadsf_update): Likewise.
Thanks.  I have checked this in.
diff mbox

Patch

diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
index d1a9159..c61107f 100644
--- a/gcc/config/arc/arc.md
+++ b/gcc/config/arc/arc.md
@@ -1254,7 +1254,7 @@ 
   [(set (match_operand:QI 3 "dest_reg_operand" "=r,r")
         (match_operator:QI 4 "any_mem_operand"
          [(plus:SI (match_operand:SI 1 "register_operand" "0,0")
-                   (match_operand:SI 2 "nonmemory_operand" "rI,Cal"))]))
+                   (match_operand:SI 2 "nonmemory_operand" "rCm2,Cal"))]))
    (set (match_operand:SI 0 "dest_reg_operand" "=r,r")
 	(plus:SI (match_dup 1) (match_dup 2)))]
   ""
@@ -1266,7 +1266,7 @@ 
   [(set (match_operand:SI 3 "dest_reg_operand" "=r,r")
 	(zero_extend:SI (match_operator:QI 4 "any_mem_operand"
 			 [(plus:SI (match_operand:SI 1 "register_operand" "0,0")
-			           (match_operand:SI 2 "nonmemory_operand" "rI,Cal"))])))
+			           (match_operand:SI 2 "nonmemory_operand" "rCm2,Cal"))])))
    (set (match_operand:SI 0 "dest_reg_operand" "=r,r")
 	(plus:SI (match_dup 1) (match_dup 2)))]
   ""
@@ -1278,7 +1278,7 @@ 
   [(set (match_operand:SI 3 "dest_reg_operand" "=r,r")
 	(sign_extend:SI (match_operator:QI 4 "any_mem_operand"
 			 [(plus:SI (match_operand:SI 1 "register_operand" "0,0")
-			           (match_operand:SI 2 "nonmemory_operand" "rI,Cal"))])))
+			           (match_operand:SI 2 "nonmemory_operand" "rCm2,Cal"))])))
    (set (match_operand:SI 0 "dest_reg_operand" "=r,r")
 	(plus:SI (match_dup 1) (match_dup 2)))]
   ""
@@ -1304,7 +1304,7 @@ 
   [(set (match_operand:HI 3 "dest_reg_operand" "=r,r")
 	(match_operator:HI 4 "any_mem_operand"
 	 [(plus:SI (match_operand:SI 1 "register_operand" "0,0")
-	           (match_operand:SI 2 "nonmemory_operand" "rI,Cal"))]))
+	           (match_operand:SI 2 "nonmemory_operand" "rCm2,Cal"))]))
    (set (match_operand:SI 0 "dest_reg_operand" "=w,w")
 	(plus:SI (match_dup 1) (match_dup 2)))]
   ""
@@ -1316,7 +1316,7 @@ 
   [(set (match_operand:SI 3 "dest_reg_operand" "=r,r")
 	(zero_extend:SI (match_operator:HI 4 "any_mem_operand"
 			 [(plus:SI (match_operand:SI 1 "register_operand" "0,0")
-			           (match_operand:SI 2 "nonmemory_operand" "rI,Cal"))])))
+			           (match_operand:SI 2 "nonmemory_operand" "rCm2,Cal"))])))
    (set (match_operand:SI 0 "dest_reg_operand" "=r,r")
 	(plus:SI (match_dup 1) (match_dup 2)))]
   ""
@@ -1329,7 +1329,7 @@ 
   [(set (match_operand:SI 3 "dest_reg_operand" "=r,r")
 	(sign_extend:SI (match_operator:HI 4 "any_mem_operand"
 			 [(plus:SI (match_operand:SI 1 "register_operand" "0,0")
-			           (match_operand:SI 2 "nonmemory_operand" "rI,Cal"))])))
+			           (match_operand:SI 2 "nonmemory_operand" "rCm2,Cal"))])))
    (set (match_operand:SI 0 "dest_reg_operand" "=w,w")
 	(plus:SI (match_dup 1) (match_dup 2)))]
   ""
@@ -1354,7 +1354,7 @@ 
   [(set (match_operand:SI 3 "dest_reg_operand" "=r,r")
 	(match_operator:SI 4 "any_mem_operand"
 	 [(plus:SI (match_operand:SI 1 "register_operand" "0,0")
-	           (match_operand:SI 2 "nonmemory_operand" "rI,Cal"))]))
+	           (match_operand:SI 2 "nonmemory_operand" "rCm2,Cal"))]))
    (set (match_operand:SI 0 "dest_reg_operand" "=w,w")
 	(plus:SI (match_dup 1) (match_dup 2)))]
   ""
@@ -1378,7 +1378,7 @@ 
   [(set (match_operand:SF 3 "dest_reg_operand" "=r,r")
 	(match_operator:SF 4 "any_mem_operand"
 	 [(plus:SI (match_operand:SI 1 "register_operand" "0,0")
-	           (match_operand:SI 2 "nonmemory_operand" "rI,Cal"))]))
+	           (match_operand:SI 2 "nonmemory_operand" "rCm2,Cal"))]))
    (set (match_operand:SI 0 "dest_reg_operand" "=w,w")
 	(plus:SI (match_dup 1) (match_dup 2)))]
   ""