From patchwork Wed Apr 6 12:54:31 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jakub Jelinek X-Patchwork-Id: 607005 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3qg5KQ5QsFz9t3h for ; Wed, 6 Apr 2016 22:54:49 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=cDspa3Q7; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:subject:message-id:reply-to:mime-version:content-type; q=dns; s=default; b=bR7nFYHyi9tLnsAa5MjIFcQEM/bYXOduv6i1+X2kb4H sYyMUwj+zJMh52RF86dZBLVmvbasHnUDKr2NSI80hkqMybmoyqIdvlXqkfzzhtRe mPQGzUSRrkfy2WbIxdZbIvRXUCgLmn8A1lrOoN3NXpC7hBDw2apQNxR+hUSPwyJk = DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:subject:message-id:reply-to:mime-version:content-type; s=default; bh=VTCPUY/6BCXxLS+2BYEuY8Lo6sI=; b=cDspa3Q7TZq5lVL+D 0X0SIcY0Km2buQDvRRI3PUSc2itkwGMshDCMEh0Z7w+QrKG+yrMeiXzDDR+tZERL YFyk6yPTbKlN3dQy9LLeG7kLYfTU7hR/LNt/7wab9EC2g3Cja0oCv3ThTxPGo4jd n/zyMdYFTN+OHTbTUJ+uWVIF4k= Received: (qmail 101855 invoked by alias); 6 Apr 2016 12:54:41 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 101843 invoked by uid 89); 6 Apr 2016 12:54:41 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.9 required=5.0 tests=BAYES_00, RP_MATCHES_RCVD, SPF_HELO_PASS autolearn=ham version=3.3.2 spammy=986, 14116, 1978, 856 X-HELO: mx1.redhat.com Received: from mx1.redhat.com (HELO mx1.redhat.com) (209.132.183.28) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-GCM-SHA384 encrypted) ESMTPS; Wed, 06 Apr 2016 12:54:37 +0000 Received: from int-mx14.intmail.prod.int.phx2.redhat.com (int-mx14.intmail.prod.int.phx2.redhat.com [10.5.11.27]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id E3CD97F6B4 for ; Wed, 6 Apr 2016 12:54:35 +0000 (UTC) Received: from tucnak.zalov.cz (ovpn-113-22.phx2.redhat.com [10.3.113.22]) by int-mx14.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id u36CsYpi027780 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO) for ; Wed, 6 Apr 2016 08:54:35 -0400 Received: from tucnak.zalov.cz (localhost [127.0.0.1]) by tucnak.zalov.cz (8.15.2/8.15.2) with ESMTP id u36CsWS7000805 for ; Wed, 6 Apr 2016 14:54:33 +0200 Received: (from jakub@localhost) by tucnak.zalov.cz (8.15.2/8.15.2/Submit) id u36CsVuA000804 for gcc-patches@gcc.gnu.org; Wed, 6 Apr 2016 14:54:31 +0200 Date: Wed, 6 Apr 2016 14:54:31 +0200 From: Jakub Jelinek To: gcc-patches@gcc.gnu.org Subject: [committed] OpenMP declare simd ABI changes on x86_64/i686 Message-ID: <20160406125431.GX19207@tucnak.redhat.com> Reply-To: Jakub Jelinek MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.5.24 (2015-08-30) X-IsSubscribed: yes Hi! As we already have some declare simd ABI changes in GCC 6 (mangling of the various linear clause kinds), and as glibc uses the AVX512F stuff in, I've decided to commit following ABI changes right now rather than waiting for GCC 7. The changes are: 1) for AVX2, functions with {{un,}signed ,}char characteristic type without simdlen clause are now using simdlen of 32 rather than 16 2) there are new AVX512F entrypoints, with mangling character e, that pass/return values in __attribute__((vector_size (64))) vectors (both integer and floating point) 3) the fuzzy part is what to do with functions with explicit rather than implicit simdlen clause if it is > 16; we certainly need some upper bound, the spec doesn't say anything, and I don't have recent enough ICC to check what is used right now Bootstrapped/regtested on x86_64-linux and i686-linux, committed to trunk. I'll try to coordinate with Intel about 3) as well as the default alignment if aligned clause is used on declare simd without any explicit alignment. 2016-04-06 Jakub Jelinek * config/i386/i386.c (ix86_simd_clone_compute_vecsize_and_simdlen): Add support for AVX512F clones, include them by default for exported OpenMP declare simd functions. For AVX2 allow simdlen 32 and use it if charasteric type is 8-bit, for AVX512F allow simdlen up to 128. * lib/target-supports.exp (check_effective_target_vect_simd_clones): Check for avx512f effective targets instead of avx2. * gcc.dg/gomp/declare-simd-1.c: Add scan-assembler-times directives for AVX512F clones. * gcc.dg/gomp/declare-simd-3.c: Likewise. * g++.dg/gomp/declare-simd-1.C: Likewise. * g++.dg/gomp/declare-simd-3.C: Likewise. * g++.dg/gomp/declare-simd-4.C: Likewise. Jakub --- gcc/config/i386/i386.c.jj 2016-04-01 17:21:31.000000000 +0200 +++ gcc/config/i386/i386.c 2016-04-06 12:05:30.381913719 +0200 @@ -53761,7 +53761,7 @@ ix86_simd_clone_compute_vecsize_and_simd if (clonei->simdlen && (clonei->simdlen < 2 - || clonei->simdlen > 16 + || clonei->simdlen > 128 || (clonei->simdlen & (clonei->simdlen - 1)) != 0)) { warning_at (DECL_SOURCE_LOCATION (node->decl), 0, @@ -53819,7 +53819,9 @@ ix86_simd_clone_compute_vecsize_and_simd { /* If the function isn't exported, we can pick up just one ISA for the clones. */ - if (TARGET_AVX2) + if (TARGET_AVX512F) + clonei->vecsize_mangle = 'e'; + else if (TARGET_AVX2) clonei->vecsize_mangle = 'd'; else if (TARGET_AVX) clonei->vecsize_mangle = 'c'; @@ -53829,8 +53831,8 @@ ix86_simd_clone_compute_vecsize_and_simd } else { - clonei->vecsize_mangle = "bcd"[num]; - ret = 3; + clonei->vecsize_mangle = "bcde"[num]; + ret = 4; } switch (clonei->vecsize_mangle) { @@ -53846,6 +53848,10 @@ ix86_simd_clone_compute_vecsize_and_simd clonei->vecsize_int = 256; clonei->vecsize_float = 256; break; + case 'e': + clonei->vecsize_int = 512; + clonei->vecsize_float = 512; + break; } if (clonei->simdlen == 0) { @@ -53854,9 +53860,24 @@ ix86_simd_clone_compute_vecsize_and_simd else clonei->simdlen = clonei->vecsize_float; clonei->simdlen /= GET_MODE_BITSIZE (TYPE_MODE (base_type)); - if (clonei->simdlen > 16) - clonei->simdlen = 16; } + else if (clonei->simdlen > 16) + switch (clonei->vecsize_int) + { + case 512: + /* For AVX512-F, support VLEN up to 128. */ + break; + case 256: + /* For AVX2, support VLEN up to 32. */ + if (clonei->simdlen <= 32) + break; + /* FALLTHRU */ + default: + /* Otherwise, support VLEN up to 16. */ + warning_at (DECL_SOURCE_LOCATION (node->decl), 0, + "unsupported simdlen %d", clonei->simdlen); + return 0; + } return ret; } @@ -53881,6 +53902,10 @@ ix86_simd_clone_adjust (struct cgraph_no if (!TARGET_AVX2) str = "avx2"; break; + case 'e': + if (!TARGET_AVX512F) + str = "avx512f"; + break; default: gcc_unreachable (); } @@ -53920,6 +53945,10 @@ ix86_simd_clone_usable (struct cgraph_no if (!TARGET_AVX2) return -1; return 0; + case 'e': + if (!TARGET_AVX512F) + return -1; + return 0; default: gcc_unreachable (); } --- gcc/testsuite/lib/target-supports.exp.jj 2016-03-23 19:25:53.000000000 +0100 +++ gcc/testsuite/lib/target-supports.exp 2016-04-06 11:19:06.398694815 +0200 @@ -2603,7 +2603,7 @@ proc check_effective_target_vect_simd_cl # avx2 clone. Only the right clone for the specified arch will be # chosen, but still we need to at least be able to assemble # avx2. - if { [check_effective_target_avx2] } { + if { [check_effective_target_avx512f] } { set et_vect_simd_clones_saved 1 } } --- gcc/testsuite/gcc.dg/gomp/declare-simd-1.c.jj 2015-11-05 16:03:53.000000000 +0100 +++ gcc/testsuite/gcc.dg/gomp/declare-simd-1.c 2016-04-06 12:09:31.743657883 +0200 @@ -19,6 +19,8 @@ int f2 (int a, int *b, int c) /* { dg-final { scan-assembler-times "_ZGVcN8uva32l4_f2:" 1 { target { i?86-*-* x86_64-*-* } } } } */ /* { dg-final { scan-assembler-times "_ZGVdM8uva32l4_f2:" 1 { target { i?86-*-* x86_64-*-* } } } } */ /* { dg-final { scan-assembler-times "_ZGVdN8uva32l4_f2:" 1 { target { i?86-*-* x86_64-*-* } } } } */ +/* { dg-final { scan-assembler-times "_ZGVeM8uva32l4_f2:" 1 { target { i?86-*-* x86_64-*-* } } } } */ +/* { dg-final { scan-assembler-times "_ZGVeN8uva32l4_f2:" 1 { target { i?86-*-* x86_64-*-* } } } } */ #pragma omp declare simd uniform (a) aligned (b : 8 * sizeof (long long)) linear (c : 4) simdlen (8) __extension__ @@ -53,6 +55,8 @@ f7 (int x) /* { dg-final { scan-assembler-times "_ZGVcN16v_f7:" 1 { target { i?86-*-* x86_64-*-* } } } } */ /* { dg-final { scan-assembler-times "_ZGVdM16v_f7:" 1 { target { i?86-*-* x86_64-*-* } } } } */ /* { dg-final { scan-assembler-times "_ZGVdN16v_f7:" 1 { target { i?86-*-* x86_64-*-* } } } } */ +/* { dg-final { scan-assembler-times "_ZGVeM16v_f7:" 1 { target { i?86-*-* x86_64-*-* } } } } */ +/* { dg-final { scan-assembler-times "_ZGVeN16v_f7:" 1 { target { i?86-*-* x86_64-*-* } } } } */ int f9 (int x) @@ -82,6 +86,8 @@ f13 (int c; int *b; int a; int a, int *b /* { dg-final { scan-assembler-times "_ZGVcN8uva32l4_f13:" 1 { target { i?86-*-* x86_64-*-* } } } } */ /* { dg-final { scan-assembler-times "_ZGVdM8uva32l4_f13:" 1 { target { i?86-*-* x86_64-*-* } } } } */ /* { dg-final { scan-assembler-times "_ZGVdN8uva32l4_f13:" 1 { target { i?86-*-* x86_64-*-* } } } } */ +/* { dg-final { scan-assembler-times "_ZGVeM8uva32l4_f13:" 1 { target { i?86-*-* x86_64-*-* } } } } */ +/* { dg-final { scan-assembler-times "_ZGVeN8uva32l4_f13:" 1 { target { i?86-*-* x86_64-*-* } } } } */ #pragma omp declare simd uniform (a) aligned (b : 8 * sizeof (int)) linear (c : 4) simdlen (8) int @@ -98,6 +104,8 @@ f14 (a, b, c) /* { dg-final { scan-assembler-times "_ZGVcN8uva32l4_f14:" 1 { target { i?86-*-* x86_64-*-* } } } } */ /* { dg-final { scan-assembler-times "_ZGVdM8uva32l4_f14:" 1 { target { i?86-*-* x86_64-*-* } } } } */ /* { dg-final { scan-assembler-times "_ZGVdN8uva32l4_f14:" 1 { target { i?86-*-* x86_64-*-* } } } } */ +/* { dg-final { scan-assembler-times "_ZGVeM8uva32l4_f14:" 1 { target { i?86-*-* x86_64-*-* } } } } */ +/* { dg-final { scan-assembler-times "_ZGVeN8uva32l4_f14:" 1 { target { i?86-*-* x86_64-*-* } } } } */ #pragma omp declare simd uniform (a) aligned (b : 8 * sizeof (int)) linear (c : 4) simdlen (8) int @@ -112,6 +120,8 @@ f15 (int a, int *b, int c) /* { dg-final { scan-assembler-times "_ZGVcN8uva32l4_f15:" 1 { target { i?86-*-* x86_64-*-* } } } } */ /* { dg-final { scan-assembler-times "_ZGVdM8uva32l4_f15:" 1 { target { i?86-*-* x86_64-*-* } } } } */ /* { dg-final { scan-assembler-times "_ZGVdN8uva32l4_f15:" 1 { target { i?86-*-* x86_64-*-* } } } } */ +/* { dg-final { scan-assembler-times "_ZGVeM8uva32l4_f15:" 1 { target { i?86-*-* x86_64-*-* } } } } */ +/* { dg-final { scan-assembler-times "_ZGVeN8uva32l4_f15:" 1 { target { i?86-*-* x86_64-*-* } } } } */ #pragma omp declare simd uniform (d) aligned (e : 8 * sizeof (int)) linear (f : 4) simdlen (8) int f15 (int d, int *e, int f); @@ -131,12 +141,16 @@ int f17 (int g, long *h) /* { dg-final { scan-assembler-times "_ZGVcN4l20va8_f17:" 1 { target { { i?86-*-* x86_64-*-* } && lp64 } } } } */ /* { dg-final { scan-assembler-times "_ZGVdM4l20va8_f17:" 1 { target { { i?86-*-* x86_64-*-* } && lp64 } } } } */ /* { dg-final { scan-assembler-times "_ZGVdN4l20va8_f17:" 1 { target { { i?86-*-* x86_64-*-* } && lp64 } } } } */ +/* { dg-final { scan-assembler-times "_ZGVeM4l20va8_f17:" 1 { target { { i?86-*-* x86_64-*-* } && lp64 } } } } */ +/* { dg-final { scan-assembler-times "_ZGVeN4l20va8_f17:" 1 { target { { i?86-*-* x86_64-*-* } && lp64 } } } } */ /* { dg-final { scan-assembler-times "_ZGVbM4l12va4_f17:" 1 { target { { i?86-*-* x86_64-*-* } && ilp32 } } } } */ /* { dg-final { scan-assembler-times "_ZGVbN4l12va4_f17:" 1 { target { { i?86-*-* x86_64-*-* } && ilp32 } } } } */ /* { dg-final { scan-assembler-times "_ZGVcM4l12va4_f17:" 1 { target { { i?86-*-* x86_64-*-* } && ilp32 } } } } */ /* { dg-final { scan-assembler-times "_ZGVcN4l12va4_f17:" 1 { target { { i?86-*-* x86_64-*-* } && ilp32 } } } } */ /* { dg-final { scan-assembler-times "_ZGVdM4l12va4_f17:" 1 { target { { i?86-*-* x86_64-*-* } && ilp32 } } } } */ /* { dg-final { scan-assembler-times "_ZGVdN4l12va4_f17:" 1 { target { { i?86-*-* x86_64-*-* } && ilp32 } } } } */ +/* { dg-final { scan-assembler-times "_ZGVeM4l12va4_f17:" 1 { target { { i?86-*-* x86_64-*-* } && ilp32 } } } } */ +/* { dg-final { scan-assembler-times "_ZGVeN4l12va4_f17:" 1 { target { { i?86-*-* x86_64-*-* } && ilp32 } } } } */ #pragma omp declare simd aligned (i : sizeof (*i)) linear (j : 2 * sizeof (i[0]) + sizeof (j)) simdlen (4) int @@ -153,9 +167,13 @@ f18 (j, i) /* { dg-final { scan-assembler-times "_ZGVcN4l20va8_f18:" 1 { target { { i?86-*-* x86_64-*-* } && lp64 } } } } */ /* { dg-final { scan-assembler-times "_ZGVdM4l20va8_f18:" 1 { target { { i?86-*-* x86_64-*-* } && lp64 } } } } */ /* { dg-final { scan-assembler-times "_ZGVdN4l20va8_f18:" 1 { target { { i?86-*-* x86_64-*-* } && lp64 } } } } */ +/* { dg-final { scan-assembler-times "_ZGVeM4l20va8_f18:" 1 { target { { i?86-*-* x86_64-*-* } && lp64 } } } } */ +/* { dg-final { scan-assembler-times "_ZGVeN4l20va8_f18:" 1 { target { { i?86-*-* x86_64-*-* } && lp64 } } } } */ /* { dg-final { scan-assembler-times "_ZGVbM4l12va4_f18:" 1 { target { { i?86-*-* x86_64-*-* } && ilp32 } } } } */ /* { dg-final { scan-assembler-times "_ZGVbN4l12va4_f18:" 1 { target { { i?86-*-* x86_64-*-* } && ilp32 } } } } */ /* { dg-final { scan-assembler-times "_ZGVcM4l12va4_f18:" 1 { target { { i?86-*-* x86_64-*-* } && ilp32 } } } } */ /* { dg-final { scan-assembler-times "_ZGVcN4l12va4_f18:" 1 { target { { i?86-*-* x86_64-*-* } && ilp32 } } } } */ /* { dg-final { scan-assembler-times "_ZGVdM4l12va4_f18:" 1 { target { { i?86-*-* x86_64-*-* } && ilp32 } } } } */ /* { dg-final { scan-assembler-times "_ZGVdN4l12va4_f18:" 1 { target { { i?86-*-* x86_64-*-* } && ilp32 } } } } */ +/* { dg-final { scan-assembler-times "_ZGVeM4l12va4_f18:" 1 { target { { i?86-*-* x86_64-*-* } && ilp32 } } } } */ +/* { dg-final { scan-assembler-times "_ZGVeN4l12va4_f18:" 1 { target { { i?86-*-* x86_64-*-* } && ilp32 } } } } */ --- gcc/testsuite/gcc.dg/gomp/declare-simd-3.c.jj 2015-11-05 16:03:53.000000000 +0100 +++ gcc/testsuite/gcc.dg/gomp/declare-simd-3.c 2016-04-06 12:29:11.307746215 +0200 @@ -11,6 +11,8 @@ f1 (int *p, int *q, short *s) /* { dg-final { scan-assembler-times "_ZGVcN4l4ln4ln6_f1:" 1 { target { i?86-*-* x86_64-*-* } } } } */ /* { dg-final { scan-assembler-times "_ZGVdM8l4ln4ln6_f1:" 1 { target { i?86-*-* x86_64-*-* } } } } */ /* { dg-final { scan-assembler-times "_ZGVdN8l4ln4ln6_f1:" 1 { target { i?86-*-* x86_64-*-* } } } } */ +/* { dg-final { scan-assembler-times "_ZGVeM16l4ln4ln6_f1:" 1 { target { i?86-*-* x86_64-*-* } } } } */ +/* { dg-final { scan-assembler-times "_ZGVeN16l4ln4ln6_f1:" 1 { target { i?86-*-* x86_64-*-* } } } } */ #pragma omp declare simd linear(p:s) linear(q:t) uniform (s) linear(r:s) notinbranch simdlen(8) uniform(t) int @@ -22,3 +24,4 @@ f2 (int *p, short *q, int s, int r, int /* { dg-final { scan-assembler-times "_ZGVbN8ls2ls4uls2u_f2:" 1 { target { i?86-*-* x86_64-*-* } } } } */ /* { dg-final { scan-assembler-times "_ZGVcN8ls2ls4uls2u_f2:" 1 { target { i?86-*-* x86_64-*-* } } } } */ /* { dg-final { scan-assembler-times "_ZGVdN8ls2ls4uls2u_f2:" 1 { target { i?86-*-* x86_64-*-* } } } } */ +/* { dg-final { scan-assembler-times "_ZGVeN8ls2ls4uls2u_f2:" 1 { target { i?86-*-* x86_64-*-* } } } } */ --- gcc/testsuite/g++.dg/gomp/declare-simd-1.C.jj 2015-11-05 16:03:53.000000000 +0100 +++ gcc/testsuite/g++.dg/gomp/declare-simd-1.C 2016-04-06 12:20:52.494474931 +0200 @@ -20,6 +20,8 @@ int f2 (int a, int *b, int c) // { dg-final { scan-assembler-times "_ZGVcN8uva32l4__Z2f2iPii:" 1 { target { i?86-*-* x86_64-*-* } } } } // { dg-final { scan-assembler-times "_ZGVdM8uva32l4__Z2f2iPii:" 1 { target { i?86-*-* x86_64-*-* } } } } // { dg-final { scan-assembler-times "_ZGVdN8uva32l4__Z2f2iPii:" 1 { target { i?86-*-* x86_64-*-* } } } } +// { dg-final { scan-assembler-times "_ZGVeM8uva32l4__Z2f2iPii:" 1 { target { i?86-*-* x86_64-*-* } } } } +// { dg-final { scan-assembler-times "_ZGVeN8uva32l4__Z2f2iPii:" 1 { target { i?86-*-* x86_64-*-* } } } } #pragma omp declare simd uniform (c) aligned (b : 4 * sizeof (int)) linear (a : 4) simdlen (4) template @@ -85,6 +87,8 @@ namespace N1 // { dg-final { scan-assembler-times "_ZGVcN2va16__ZN2N12N23f10EPx:" 1 { target { i?86-*-* x86_64-*-* } } } } // { dg-final { scan-assembler-times "_ZGVdM2va16__ZN2N12N23f10EPx:" 1 { target { i?86-*-* x86_64-*-* } } } } // { dg-final { scan-assembler-times "_ZGVdN2va16__ZN2N12N23f10EPx:" 1 { target { i?86-*-* x86_64-*-* } } } } +// { dg-final { scan-assembler-times "_ZGVeM2va16__ZN2N12N23f10EPx:" 1 { target { i?86-*-* x86_64-*-* } } } } +// { dg-final { scan-assembler-times "_ZGVeN2va16__ZN2N12N23f10EPx:" 1 { target { i?86-*-* x86_64-*-* } } } } struct A { @@ -193,6 +197,8 @@ int B::f25<7> (int a, int *b, int c // { dg-final { scan-assembler-times "_ZGVcN8vuva32u__ZN1BIiE3f25ILi7EEEiiPii:" 1 { target { i?86-*-* x86_64-*-* } } } } // { dg-final { scan-assembler-times "_ZGVdM8vuva32u__ZN1BIiE3f25ILi7EEEiiPii:" 1 { target { i?86-*-* x86_64-*-* } } } } // { dg-final { scan-assembler-times "_ZGVdN8vuva32u__ZN1BIiE3f25ILi7EEEiiPii:" 1 { target { i?86-*-* x86_64-*-* } } } } +// { dg-final { scan-assembler-times "_ZGVeM8vuva32u__ZN1BIiE3f25ILi7EEEiiPii:" 1 { target { i?86-*-* x86_64-*-* } } } } +// { dg-final { scan-assembler-times "_ZGVeN8vuva32u__ZN1BIiE3f25ILi7EEEiiPii:" 1 { target { i?86-*-* x86_64-*-* } } } } #pragma omp declare simd simdlen (4) aligned (b : 8 * sizeof (int)) linear (a, c : 2) template <> @@ -208,6 +214,8 @@ int B::f26<-1> (int a, int *b, int // { dg-final { scan-assembler-times "_ZGVcN4vl2va32__ZN1BIiE3f26ILin1EEEiiPii:" 1 { target { i?86-*-* x86_64-*-* } } } } // { dg-final { scan-assembler-times "_ZGVdM4vl2va32__ZN1BIiE3f26ILin1EEEiiPii:" 1 { target { i?86-*-* x86_64-*-* } } } } // { dg-final { scan-assembler-times "_ZGVdN4vl2va32__ZN1BIiE3f26ILin1EEEiiPii:" 1 { target { i?86-*-* x86_64-*-* } } } } +// { dg-final { scan-assembler-times "_ZGVeM4vl2va32__ZN1BIiE3f26ILin1EEEiiPii:" 1 { target { i?86-*-* x86_64-*-* } } } } +// { dg-final { scan-assembler-times "_ZGVeN4vl2va32__ZN1BIiE3f26ILin1EEEiiPii:" 1 { target { i?86-*-* x86_64-*-* } } } } int f27 (int x) @@ -237,6 +245,8 @@ f30 (int x) // { dg-final { scan-assembler-times "_ZGVcN16v__Z3f30i:" 1 { target { i?86-*-* x86_64-*-* } } } } // { dg-final { scan-assembler-times "_ZGVdM16v__Z3f30i:" 1 { target { i?86-*-* x86_64-*-* } } } } // { dg-final { scan-assembler-times "_ZGVdN16v__Z3f30i:" 1 { target { i?86-*-* x86_64-*-* } } } } +// { dg-final { scan-assembler-times "_ZGVeM16v__Z3f30i:" 1 { target { i?86-*-* x86_64-*-* } } } } +// { dg-final { scan-assembler-times "_ZGVeN16v__Z3f30i:" 1 { target { i?86-*-* x86_64-*-* } } } } template struct C --- gcc/testsuite/g++.dg/gomp/declare-simd-3.C.jj 2015-11-05 16:03:53.000000000 +0100 +++ gcc/testsuite/g++.dg/gomp/declare-simd-3.C 2016-04-06 12:30:27.556717659 +0200 @@ -19,6 +19,8 @@ int f1 (int a, int b, int c, int &d, int // { dg-final { scan-assembler-times "_ZGVcN4vulLUR4__Z2f1iiiRiS_S_:" 1 { target { i?86-*-* x86_64-*-* } } } } // { dg-final { scan-assembler-times "_ZGVdM8vulLUR4__Z2f1iiiRiS_S_:" 1 { target { i?86-*-* x86_64-*-* } } } } // { dg-final { scan-assembler-times "_ZGVdN8vulLUR4__Z2f1iiiRiS_S_:" 1 { target { i?86-*-* x86_64-*-* } } } } +// { dg-final { scan-assembler-times "_ZGVeM16vulLUR4__Z2f1iiiRiS_S_:" 1 { target { i?86-*-* x86_64-*-* } } } } +// { dg-final { scan-assembler-times "_ZGVeN16vulLUR4__Z2f1iiiRiS_S_:" 1 { target { i?86-*-* x86_64-*-* } } } } #pragma omp declare simd uniform(b) linear(c, d) linear(uval(e)) linear(ref(f)) int f2 (int a, int b, int c, int &d, int &e, int &f) @@ -44,6 +46,8 @@ int f2 (int a, int b, int c, int &d, int // { dg-final { scan-assembler-times "_ZGVcN4vulLUR4__Z2f2iiiRiS_S_:" 1 { target { i?86-*-* x86_64-*-* } } } } // { dg-final { scan-assembler-times "_ZGVdM8vulLUR4__Z2f2iiiRiS_S_:" 1 { target { i?86-*-* x86_64-*-* } } } } // { dg-final { scan-assembler-times "_ZGVdN8vulLUR4__Z2f2iiiRiS_S_:" 1 { target { i?86-*-* x86_64-*-* } } } } +// { dg-final { scan-assembler-times "_ZGVeM16vulLUR4__Z2f2iiiRiS_S_:" 1 { target { i?86-*-* x86_64-*-* } } } } +// { dg-final { scan-assembler-times "_ZGVeN16vulLUR4__Z2f2iiiRiS_S_:" 1 { target { i?86-*-* x86_64-*-* } } } } #pragma omp declare simd uniform(b) linear(c, d) linear(uval(e)) linear(ref(f)) int f3 (const int a, const int b, const int c, const int &d, const int &e, const int &f) @@ -57,6 +61,8 @@ int f3 (const int a, const int b, const // { dg-final { scan-assembler-times "_ZGVcN4vulLUR4__Z2f3iiiRKiS0_S0_:" 1 { target { i?86-*-* x86_64-*-* } } } } // { dg-final { scan-assembler-times "_ZGVdM8vulLUR4__Z2f3iiiRKiS0_S0_:" 1 { target { i?86-*-* x86_64-*-* } } } } // { dg-final { scan-assembler-times "_ZGVdN8vulLUR4__Z2f3iiiRKiS0_S0_:" 1 { target { i?86-*-* x86_64-*-* } } } } +// { dg-final { scan-assembler-times "_ZGVeM16vulLUR4__Z2f3iiiRKiS0_S0_:" 1 { target { i?86-*-* x86_64-*-* } } } } +// { dg-final { scan-assembler-times "_ZGVeN16vulLUR4__Z2f3iiiRKiS0_S0_:" 1 { target { i?86-*-* x86_64-*-* } } } } #pragma omp declare simd uniform(b) linear(c, d) linear(uval(e)) linear(ref(f)) int f4 (const int a, const int b, const int c, const int &d, const int &e, const int &f) @@ -76,3 +82,5 @@ int f4 (const int a, const int b, const // { dg-final { scan-assembler-times "_ZGVcN4vulLUR4__Z2f4iiiRKiS0_S0_:" 1 { target { i?86-*-* x86_64-*-* } } } } // { dg-final { scan-assembler-times "_ZGVdM8vulLUR4__Z2f4iiiRKiS0_S0_:" 1 { target { i?86-*-* x86_64-*-* } } } } // { dg-final { scan-assembler-times "_ZGVdN8vulLUR4__Z2f4iiiRKiS0_S0_:" 1 { target { i?86-*-* x86_64-*-* } } } } +// { dg-final { scan-assembler-times "_ZGVeM16vulLUR4__Z2f4iiiRKiS0_S0_:" 1 { target { i?86-*-* x86_64-*-* } } } } +// { dg-final { scan-assembler-times "_ZGVeN16vulLUR4__Z2f4iiiRKiS0_S0_:" 1 { target { i?86-*-* x86_64-*-* } } } } --- gcc/testsuite/g++.dg/gomp/declare-simd-4.C.jj 2015-11-05 16:03:53.000000000 +0100 +++ gcc/testsuite/g++.dg/gomp/declare-simd-4.C 2016-04-06 12:31:00.121278515 +0200 @@ -11,6 +11,8 @@ f1 (int *p, int *q, short *s) // { dg-final { scan-assembler-times "_ZGVcN4l4ln4ln6__Z2f1PiS_Ps:" 1 { target { i?86-*-* x86_64-*-* } } } } // { dg-final { scan-assembler-times "_ZGVdM8l4ln4ln6__Z2f1PiS_Ps:" 1 { target { i?86-*-* x86_64-*-* } } } } // { dg-final { scan-assembler-times "_ZGVdN8l4ln4ln6__Z2f1PiS_Ps:" 1 { target { i?86-*-* x86_64-*-* } } } } +// { dg-final { scan-assembler-times "_ZGVeM16l4ln4ln6__Z2f1PiS_Ps:" 1 { target { i?86-*-* x86_64-*-* } } } } +// { dg-final { scan-assembler-times "_ZGVeN16l4ln4ln6__Z2f1PiS_Ps:" 1 { target { i?86-*-* x86_64-*-* } } } } #pragma omp declare simd linear(p:s) linear(q:t) uniform (s) linear(r:s) notinbranch simdlen(8) uniform(t) int @@ -22,6 +24,7 @@ f2 (int *p, short *q, int s, int r, int // { dg-final { scan-assembler-times "_ZGVbN8ls2ls4uls2u__Z2f2PiPsiiRi:" 1 { target { i?86-*-* x86_64-*-* } } } } // { dg-final { scan-assembler-times "_ZGVcN8ls2ls4uls2u__Z2f2PiPsiiRi:" 1 { target { i?86-*-* x86_64-*-* } } } } // { dg-final { scan-assembler-times "_ZGVdN8ls2ls4uls2u__Z2f2PiPsiiRi:" 1 { target { i?86-*-* x86_64-*-* } } } } +// { dg-final { scan-assembler-times "_ZGVeN8ls2ls4uls2u__Z2f2PiPsiiRi:" 1 { target { i?86-*-* x86_64-*-* } } } } #pragma omp declare simd linear(ref(p):s) linear(val(q):t) uniform (s) linear(uval(r):s) notinbranch simdlen(8) uniform(t) int @@ -33,3 +36,4 @@ f3 (int &p, short &q, int s, int &r, int // { dg-final { scan-assembler-times "_ZGVbN8Rs2Ls4uUs2u__Z2f3RiRsiS_S_:" 1 { target { i?86-*-* x86_64-*-* } } } } // { dg-final { scan-assembler-times "_ZGVcN8Rs2Ls4uUs2u__Z2f3RiRsiS_S_:" 1 { target { i?86-*-* x86_64-*-* } } } } // { dg-final { scan-assembler-times "_ZGVdN8Rs2Ls4uUs2u__Z2f3RiRsiS_S_:" 1 { target { i?86-*-* x86_64-*-* } } } } +// { dg-final { scan-assembler-times "_ZGVeN8Rs2Ls4uUs2u__Z2f3RiRsiS_S_:" 1 { target { i?86-*-* x86_64-*-* } } } }