@@ -16930,20 +16930,21 @@
(set_attr "mode" "<sseinsnmode>")])
(define_insn "vec_dup<mode>"
- [(set (match_operand:AVX_VEC_DUP_MODE 0 "register_operand" "=x,x,v,x")
+ [(set (match_operand:AVX_VEC_DUP_MODE 0 "register_operand" "=x,x,x,v,x")
(vec_duplicate:AVX_VEC_DUP_MODE
- (match_operand:<ssescalarmode> 1 "nonimmediate_operand" "m,m,v,?x")))]
+ (match_operand:<ssescalarmode> 1 "nonimmediate_operand" "m,m,x,v,?x")))]
"TARGET_AVX"
"@
v<sseintprefix>broadcast<bcstscalarsuff>\t{%1, %0|%0, %1}
vbroadcast<ssescalarmodesuffix>\t{%1, %0|%0, %1}
v<sseintprefix>broadcast<bcstscalarsuff>\t{%x1, %0|%0, %x1}
+ v<sseintprefix>broadcast<bcstscalarsuff>\t{%x1, %g0|%g0, %x1}
#"
[(set_attr "type" "ssemov")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "maybe_evex")
- (set_attr "isa" "avx2,noavx2,avx2,noavx2")
- (set_attr "mode" "<sseinsnmode>,V8SF,<sseinsnmode>,V8SF")])
+ (set_attr "isa" "avx2,noavx2,avx2,avx512f,noavx2")
+ (set_attr "mode" "<sseinsnmode>,V8SF,<sseinsnmode>,<sseinsnmode>,V8SF")])
(define_split
[(set (match_operand:AVX2_VEC_DUP_MODE 0 "register_operand")
new file mode 100644
@@ -0,0 +1,21 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-mavx512f -O2 -ftree-vectorize -ffixed-xmm0 -ffixed-xmm1 -ffixed-xmm2 -ffixed-xmm3 -ffixed-xmm4 -ffixed-xmm5 -ffixed-xmm6 -ffixed-xmm7 -ffixed-xmm8 -ffixed-xmm9 -ffixed-xmm10 -ffixed-xmm11 -ffixed-xmm12 -ffixed-xmm13 -ffixed-xmm14" } */
+/* { dg-final { scan-assembler-times "vbroadcastsd\[ \\t\]+(?:%xmm(?:\[0-9\]|1\[0-5\]),\[ \\t\]*%ymm(?:\[0-9\]|1\[0-5\])|%xmm\[0-9\]+,\[ \\t\]*%zmm)" 1 } } */
+
+#include <immintrin.h>
+
+register __m512d z asm ("zmm16"); /* { dg-warning "call-clobbered register used for global register variable" } */
+
+double a[10000];
+
+void foo (unsigned N)
+{
+ double d;
+ _mm_store_sd(&d, _mm256_extractf128_pd (_mm512_extractf64x4_pd (z, 0), 0));
+
+ for (int i=0; i<N; i++)
+ {
+ a[i] = d;
+ a[i] += a[i-4];
+ }
+}