diff mbox

[i386,AVX-512] Split out mask version for vec_extract_hi_<mode>.

Message ID 20151228113319.GA30297@msticlxl57.ims.intel.com
State New
Headers show

Commit Message

Kirill Yukhin Dec. 28, 2015, 1:17 p.m. UTC 
Hello,
On 02 Dec 20:00, Kirill Yukhin wrote:
> Hello,
> On 30 Nov 13:46, Kirill Yukhin wrote:
> > Hello,
> > Patch in the bottom splits masked version of vec_extract_hi_<mode>
> > to block AVX-1512VL insn generation for KNL and cures ICE on spec2k6/450.soplex.
> > 
> > Bootstrapped and regtesed.
> > 
> > If no objections - I'll commit on Wednesday.
> > 
> > gcc/
> > 	* config/i386/sse.md (define_insn "vec_extract_hi_<mode>_maskm"):
> > 	Remove "prefix_extra".
> > 	(define_insn "vec_extract_hi_<mode>_mask"): New.
> > 	(define_insn "vec_extract_hi_<mode>"): Remove masking.
> > gcc/testsuite/
> > 	* gcc.target/i386/avx512vl-vextractf32x4-1.c: Fix scan pattern.
Similar patch is needed to make spec2k6/465.tonto working for gcc-5.
Is patch in the bottom ok for  gcc-5-branch if bootstrapped and regtested?
It cures spec2k6/465.tonto illegal insn emit.

--
Thanks, K

commit 3d5942b7d30d173d7d44ceb657b6ba93212cf0af
Author: kyukhin <kyukhin@138bc75d-0d04-0410-961f-82ee72b054a4>
Date:   Wed Dec 2 11:07:42 2015 +0000

    AVX-512. Split out mask version for vec_extract_hi_<mode>.
    
    gcc/
    	* config/i386/sse.md (define_insn "vec_extract_hi_<mode>_maskm"):
    	New.
    	(define_insn "vec_extract_hi_<mode>_mask"): New.
    	(define_insn "vec_extract_hi_<mode>"): Remove masking.
    gcc/testsuite/
    	* gcc.target/i386/avx512vl-vextractf64x2-1.c: Fix scan pattern.
    	* gcc.target/i386/avx512vl-vextracti64x2-1.c: Ditto.

Comments

Jakub Jelinek Dec. 28, 2015, 1:52 p.m. UTC | #1 
On Mon, Dec 28, 2015 at 04:17:02PM +0300, Kirill Yukhin wrote:
> Hello,
> On 02 Dec 20:00, Kirill Yukhin wrote:
> > Hello,
> > On 30 Nov 13:46, Kirill Yukhin wrote:
> > > Hello,
> > > Patch in the bottom splits masked version of vec_extract_hi_<mode>
> > > to block AVX-1512VL insn generation for KNL and cures ICE on spec2k6/450.soplex.
> > > 
> > > Bootstrapped and regtesed.
> > > 
> > > If no objections - I'll commit on Wednesday.
> > > 
> > > gcc/
> > > 	* config/i386/sse.md (define_insn "vec_extract_hi_<mode>_maskm"):
> > > 	Remove "prefix_extra".
> > > 	(define_insn "vec_extract_hi_<mode>_mask"): New.
> > > 	(define_insn "vec_extract_hi_<mode>"): Remove masking.
> > > gcc/testsuite/
> > > 	* gcc.target/i386/avx512vl-vextractf32x4-1.c: Fix scan pattern.
> Similar patch is needed to make spec2k6/465.tonto working for gcc-5.
> Is patch in the bottom ok for  gcc-5-branch if bootstrapped and regtested?
> It cures spec2k6/465.tonto illegal insn emit.

Can you add a runtime testcase that would fail without the patch and succeed
with it?  Perhaps add some asms etc. to force the operands to look similarly
for RA purposes.  The patch is ok with or without that testcase, though the
testcase would be greatly appreciated.

	Jakub
diff mbox

Patch

diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index dc7f6a7..6757e56 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -7018,28 +7018,50 @@ 
   DONE;
 })
 
-(define_insn "vec_extract_hi_<mode><mask_name>"
-  [(set (match_operand:<ssehalfvecmode> 0 "<store_mask_predicate>" "=v,<store_mask_constraint>")
+(define_insn "vec_extract_hi_<mode>_maskm"
+  [(set (match_operand:<ssehalfvecmode> 0 "memory_operand" "=m")
+	(vec_merge:<ssehalfvecmode>
+	  (vec_select:<ssehalfvecmode>
+	    (match_operand:VI8F_256 1 "register_operand" "v")
+	    (parallel [(const_int 2) (const_int 3)]))
+	  (match_operand:<ssehalfvecmode> 2 "memory_operand" "0")
+	  (match_operand:<ssehalfvecmode> 3 "register_operand" "k")))]
+  "TARGET_AVX512DQ && TARGET_AVX512VL
+   && rtx_equal_p (operands[2], operands[0])"
+  "vextract<shuffletype>64x2\t{$0x1, %1, %0%{%3%}|%0%{%3%}, %1, 0x1}"
+  [(set_attr "type" "sselog1")
+   (set_attr "length_immediate" "1")
+   (set_attr "prefix" "evex")
+   (set_attr "mode" "<sseinsnmode>")])
+
+(define_insn "vec_extract_hi_<mode>_mask"
+  [(set (match_operand:<ssehalfvecmode> 0 "register_operand" "=v")
+	(vec_merge:<ssehalfvecmode>
+	  (vec_select:<ssehalfvecmode>
+	    (match_operand:VI8F_256 1 "register_operand" "v")
+	    (parallel [(const_int 2) (const_int 3)]))
+	  (match_operand:<ssehalfvecmode> 2 "vector_move_operand" "0C")
+	  (match_operand:<avx512fmaskmode> 3 "register_operand" "Yk")))]
+  "TARGET_AVX512VL && TARGET_AVX512DQ"
+  "vextract<shuffletype>64x2\t{$0x1, %1, %0%{%3%}%N2|%0%{%3%}%N2, %1, 0x1}"
+  [(set_attr "type" "sselog1")
+   (set_attr "length_immediate" "1")
+   (set_attr "prefix" "evex")
+   (set_attr "mode" "<sseinsnmode>")])
+
+(define_insn "vec_extract_hi_<mode>"
+  [(set (match_operand:<ssehalfvecmode> 0 "nonimmediate_operand" "=xm, vm")
 	(vec_select:<ssehalfvecmode>
-	  (match_operand:VI8F_256 1 "register_operand" "v,v")
+	  (match_operand:VI8F_256 1 "register_operand" "x, v")
 	  (parallel [(const_int 2) (const_int 3)])))]
-  "TARGET_AVX && <mask_avx512vl_condition> && <mask_avx512dq_condition>"
-{
-  if (TARGET_AVX512VL)
-  {
-    if (TARGET_AVX512DQ)
-      return "vextract<shuffletype>64x2\t{$0x1, %1, %0<mask_operand2>|%0<mask_operand2>, %1, 0x1}";
-    else
-      return "vextract<shuffletype>32x4\t{$0x1, %1, %0|%0, %1, 0x1}";
-  }
-  else
-    return "vextract<i128>\t{$0x1, %1, %0|%0, %1, 0x1}";
-}
-  [(set_attr "type" "sselog")
-   (set_attr "prefix_extra" "1")
+  "TARGET_AVX"
+  "@
+    vextract<i128>\t{$0x1, %1, %0|%0, %1, 0x1}
+    vextract<shuffletype>64x2\t{$0x1, %1, %0|%0, %1, 0x1}"
+  [(set_attr "isa" "*, avx512dq")
+   (set_attr "prefix" "vex, evex")
+   (set_attr "type" "sselog1")
    (set_attr "length_immediate" "1")
-   (set_attr "memory" "none,store")
-   (set_attr "prefix" "vex")
    (set_attr "mode" "<sseinsnmode>")])
 
 (define_split
diff --git a/gcc/testsuite/gcc.target/i386/avx512dq-vextractf64x2-1.c b/gcc/testsuite/gcc.target/i386/avx512dq-vextractf64x2-1.c
index c8cce51..dd7e30b 100644
--- a/gcc/testsuite/gcc.target/i386/avx512dq-vextractf64x2-1.c
+++ b/gcc/testsuite/gcc.target/i386/avx512dq-vextractf64x2-1.c
@@ -3,7 +3,7 @@ 
 /* { dg-final { scan-assembler-times "vextractf64x2\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+.{7}(?:\n|\[ \\t\]+#)"  1 } } */
 /* { dg-final { scan-assembler-times "vextractf64x2\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+.{7}\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)"  1 } } */
 /* { dg-final { scan-assembler-times "vextractf64x2\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+.{7}\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)"  1 } } */
-/* { dg-final { scan-assembler-times "vextractf64x2\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+.{7}(?:\n|\[ \\t\]+#)"  1 } } */
+/* { dg-final { scan-assembler-times "vextractf(?:128|64x2)\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+.{7}(?:\n|\[ \\t\]+#)"  1 } } */
 /* { dg-final { scan-assembler-times "vextractf64x2\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+.{7}\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)"  1 } } */
 /* { dg-final { scan-assembler-times "vextractf64x2\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+.{7}\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)"  1 } } */
 
diff --git a/gcc/testsuite/gcc.target/i386/avx512dq-vextracti64x2-1.c b/gcc/testsuite/gcc.target/i386/avx512dq-vextracti64x2-1.c
index d49b0c0..a3f3224 100644
--- a/gcc/testsuite/gcc.target/i386/avx512dq-vextracti64x2-1.c
+++ b/gcc/testsuite/gcc.target/i386/avx512dq-vextracti64x2-1.c
@@ -3,7 +3,7 @@ 
 /* { dg-final { scan-assembler-times "vextracti64x2\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+.{7}(?:\n|\[ \\t\]+#)"  1 } } */
 /* { dg-final { scan-assembler-times "vextracti64x2\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+.{7}\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)"  1 } } */
 /* { dg-final { scan-assembler-times "vextracti64x2\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+.{7}\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)"  1 } } */
-/* { dg-final { scan-assembler-times "vextracti64x2\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+.{7}(?:\n|\[ \\t\]+#)"  1 } } */
+/* { dg-final { scan-assembler-times "vextracti(?:128|64x2)\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+.{7}(?:\n|\[ \\t\]+#)"  1 } } */
 /* { dg-final { scan-assembler-times "vextracti64x2\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+.{7}\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)"  1 } } */
 /* { dg-final { scan-assembler-times "vextracti64x2\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+.{7}\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)"  1 } } */