From patchwork Tue Nov 24 00:06:19 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Meissner X-Patchwork-Id: 547785 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 5F1D31402BE for ; Tue, 24 Nov 2015 11:06:36 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=TJGkmW69; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:subject:message-id:references:mime-version:content-type :in-reply-to; q=dns; s=default; b=NAamDbJcuiWSLBqEihaTHzhsmtZI8E su/lW37f32xu84NMoE39WV1/l51f6jB9uK+d4awm3+OyNL5aR3jm6brUiIjJhWfT oJ/x2pDNcwKoZn92RBPwFW2sqpqyo3kAh6N42z0ENHR/BweJHxeutN9HrJxlRGYZ iMmSHsAevaUbA= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:subject:message-id:references:mime-version:content-type :in-reply-to; s=default; bh=na43DQCb9bBoSSfVp2FA0rTTo60=; b=TJGk mW69OTBf6xGTPh7E1lXaoIHFcrm1vEWd0GC6uIF8K/llSvUJwOyqEH7KeP8ViaAu DUIrwEzOlWBtt6CMXeUjw58Z1NeZCvHKulHjr0hIuEhtcSkdx7DI4dCA2yl93MOf JWZmwEGQDumX2091wcWGzadzZ+g92dBfbeai4dI= Received: (qmail 15809 invoked by alias); 24 Nov 2015 00:06:28 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 15794 invoked by uid 89); 24 Nov 2015 00:06:28 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=0.8 required=5.0 tests=AWL, BAYES_50, KAM_LAZY_DOMAIN_SECURITY, KAM_MANYTO autolearn=no version=3.3.2 X-HELO: e19.ny.us.ibm.com Received: from e19.ny.us.ibm.com (HELO e19.ny.us.ibm.com) (129.33.205.209) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (CAMELLIA256-SHA encrypted) ESMTPS; Tue, 24 Nov 2015 00:06:26 +0000 Received: from localhost by e19.ny.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Mon, 23 Nov 2015 19:06:22 -0500 X-IBM-Helo: d01dlp01.pok.ibm.com X-IBM-MailFrom: meissner@ibm-tiger.the-meissners.org X-IBM-RcptTo: gcc-patches@gcc.gnu.org Received: from b01cxnp22036.gho.pok.ibm.com (b01cxnp22036.gho.pok.ibm.com [9.57.198.26]) by d01dlp01.pok.ibm.com (Postfix) with ESMTP id B1BE638C8059 for ; Mon, 23 Nov 2015 19:06:21 -0500 (EST) Received: from d01av03.pok.ibm.com (d01av03.pok.ibm.com [9.56.224.217]) by b01cxnp22036.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id tAO06Lu821561582 for ; Tue, 24 Nov 2015 00:06:21 GMT Received: from d01av03.pok.ibm.com (localhost [127.0.0.1]) by d01av03.pok.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id tAO06LWK025843 for ; Mon, 23 Nov 2015 19:06:21 -0500 Received: from ibm-tiger.the-meissners.org (dhcp-9-32-77-111.usma.ibm.com [9.32.77.111]) by d01av03.pok.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id tAO06KpW025570; Mon, 23 Nov 2015 19:06:20 -0500 Received: by ibm-tiger.the-meissners.org (Postfix, from userid 500) id 89EC545F60; Mon, 23 Nov 2015 19:06:19 -0500 (EST) Date: Mon, 23 Nov 2015 19:06:19 -0500 From: Michael Meissner To: Michael Meissner , David Edelsohn , Richard Biener , Segher Boessenkool , "William J. Schmidt" , GCC Patches Subject: Re: [PATCH] lround for PowerPC Message-ID: <20151124000619.GA12855@ibm-tiger.the-meissners.org> Mail-Followup-To: Michael Meissner , David Edelsohn , Richard Biener , Segher Boessenkool , "William J. Schmidt" , GCC Patches References: <20151123215623.GA21427@ibm-tiger.the-meissners.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20151123215623.GA21427@ibm-tiger.the-meissners.org> User-Agent: Mutt/1.5.20 (2009-12-10) X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 15112400-0057-0000-0000-0000028D92AA X-IsSubscribed: yes Segher Boessenkool reminded me that the lround define_expand should not have the wa and =d constraints. This patch fixes that problem. The little endian power8 system has passed the bootstrap and make check tests. The big endian power7 system is chugging away on the stage2 build if I use a more recent compiler than the host compiler (both trunk without the patches and with the patches failed in the same way). Obviously we need to dig into that failure. 2015-11-23 David Edelsohn Michael Meissner * config/rs6000/rs6000.md (UNSPEC_XSRDPI): New unspec. (Fv2): New mode attribute to be used when ISA 2.06 instructions are used on SF/DF values. (abs2_fpr): Use instead of . (nabs2_fpr): Likewise. (neg2_fpr): Likewise. (copysign3_fcpsgn): Likewise. (smax3_vsx): Likewise. (smin3_vsx): Likewise. (floatsi2_lfiwax): Likewise. (floatunssi2_lfiwz): Likewise. (fctiwz_): Likewise. (fctiwuz_): Likewise. (btrunc2): Likewise. (ceil2): Likewise. (floor2): Likewise. (xsrdpi): Add support for the lround function. (lround2): Likewise. Index: gcc/config/rs6000/rs6000.md =================================================================== --- gcc/config/rs6000/rs6000.md (revision 230768) +++ gcc/config/rs6000/rs6000.md (working copy) @@ -77,6 +77,7 @@ (define_c_enum "unspec" UNSPEC_FRIN UNSPEC_FRIP UNSPEC_FRIZ + UNSPEC_XSRDPI UNSPEC_LD_MPIC ; load_macho_picbase UNSPEC_RELD_MPIC ; re-load_macho_picbase UNSPEC_MPIC_CORRECT ; macho_correct_pic @@ -491,9 +492,17 @@ (define_mode_attr Fvsx [(SF "sp") (DF " ; SF/DF constraint for arithmetic on traditional floating point registers (define_mode_attr Ff [(SF "f") (DF "d") (DI "d")]) -; SF/DF constraint for arithmetic on VSX registers +; SF/DF constraint for arithmetic on VSX registers. This is intended to be +; used for DFmode instructions added in ISA 2.06 (power7) and SFmode +; instructions added in ISA 2.07 (power8) (define_mode_attr Fv [(SF "wy") (DF "ws") (DI "wi")]) +; SF/DF constraint for arithmetic on VSX registers using instructions added in +; ISA 2.06 (power7). This includes instructions that normally target DF mode, +; but are used on SFmode, since internally SFmode values are kept in the DFmode +; format. +(define_mode_attr Fv2 [(SF "ww") (DF "ws") (DI "wi")]) + ; SF/DF constraint for arithmetic on altivec registers (define_mode_attr Fa [(SF "wu") (DF "wv")]) @@ -4299,8 +4308,8 @@ (define_expand "abs2" "") (define_insn "*abs2_fpr" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,") - (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" ",")))] + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,") + (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" ",")))] "TARGET__FPR" "@ fabs %0,%1 @@ -4309,10 +4318,10 @@ (define_insn "*abs2_fpr" (set_attr "fp_type" "fp_addsub_")]) (define_insn "*nabs2_fpr" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,") + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,") (neg:SFDF (abs:SFDF - (match_operand:SFDF 1 "gpc_reg_operand" ","))))] + (match_operand:SFDF 1 "gpc_reg_operand" ","))))] "TARGET__FPR" "@ fnabs %0,%1 @@ -4327,8 +4336,8 @@ (define_expand "neg2" "") (define_insn "*neg2_fpr" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,") - (neg:SFDF (match_operand:SFDF 1 "gpc_reg_operand" ",")))] + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,") + (neg:SFDF (match_operand:SFDF 1 "gpc_reg_operand" ",")))] "TARGET__FPR" "@ fneg %0,%1 @@ -4557,9 +4566,9 @@ (define_expand "copysign3" ;; Use an unspec rather providing an if-then-else in RTL, to prevent the ;; compiler from optimizing -0.0 (define_insn "copysign3_fcpsgn" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,") - (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" ",") - (match_operand:SFDF 2 "gpc_reg_operand" ",")] + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,") + (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" ",") + (match_operand:SFDF 2 "gpc_reg_operand" ",")] UNSPEC_COPYSIGN))] "TARGET__FPR && TARGET_CMPB" "@ @@ -4593,9 +4602,9 @@ (define_expand "smax3" }) (define_insn "*smax3_vsx" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,") - (smax:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%,") - (match_operand:SFDF 2 "gpc_reg_operand" ",")))] + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,") + (smax:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%,") + (match_operand:SFDF 2 "gpc_reg_operand" ",")))] "TARGET__FPR && TARGET_VSX" "xsmaxdp %x0,%x1,%x2" [(set_attr "type" "fp")]) @@ -4613,9 +4622,9 @@ (define_expand "smin3" }) (define_insn "*smin3_vsx" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,") - (smin:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%,") - (match_operand:SFDF 2 "gpc_reg_operand" ",")))] + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,") + (smin:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%,") + (match_operand:SFDF 2 "gpc_reg_operand" ",")))] "TARGET__FPR && TARGET_VSX" "xsmindp %x0,%x1,%x2" [(set_attr "type" "fp")]) @@ -4836,7 +4845,7 @@ (define_insn "lfiwax" ; not be needed and also in case the insns are deleted as dead code. (define_insn_and_split "floatsi2_lfiwax" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "=") + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=") (float:SFDF (match_operand:SI 1 "nonimmediate_operand" "r"))) (clobber (match_scratch:DI 2 "=wj"))] "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX @@ -4911,7 +4920,7 @@ (define_insn "lfiwzx" [(set_attr "type" "fpload,fpload,mftgpr")]) (define_insn_and_split "floatunssi2_lfiwzx" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "=") + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=") (unsigned_float:SFDF (match_operand:SI 1 "nonimmediate_operand" "r"))) (clobber (match_scratch:DI 2 "=wj"))] "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX @@ -5346,7 +5355,7 @@ (define_insn "*fixuns_truncdi2_fct ; before the instruction. (define_insn "fctiwz_" [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wi") - (unspec:DI [(fix:SI (match_operand:SFDF 1 "gpc_reg_operand" ","))] + (unspec:DI [(fix:SI (match_operand:SFDF 1 "gpc_reg_operand" ","))] UNSPEC_FCTIWZ))] "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" "@ @@ -5357,7 +5366,7 @@ (define_insn "fctiwz_" (define_insn "fctiwuz_" [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wi") (unspec:DI [(unsigned_fix:SI - (match_operand:SFDF 1 "gpc_reg_operand" ","))] + (match_operand:SFDF 1 "gpc_reg_operand" ","))] UNSPEC_FCTIWUZ))] "TARGET_HARD_FLOAT && TARGET_FPRS && && TARGET_FCTIWUZ" "@ @@ -5458,8 +5467,8 @@ (define_insn "lrintdi2" [(set_attr "type" "fp")]) (define_insn "btrunc2" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,") - (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" ",")] + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,") + (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" ",")] UNSPEC_FRIZ))] "TARGET__FPR && TARGET_FPRND" "@ @@ -5469,8 +5478,8 @@ (define_insn "btrunc2" (set_attr "fp_type" "fp_addsub_")]) (define_insn "ceil2" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,") - (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" ",")] + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,") + (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" ",")] UNSPEC_FRIP))] "TARGET__FPR && TARGET_FPRND" "@ @@ -5480,8 +5489,8 @@ (define_insn "ceil2" (set_attr "fp_type" "fp_addsub_")]) (define_insn "floor2" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,") - (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" ",")] + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,") + (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" ",")] UNSPEC_FRIM))] "TARGET__FPR && TARGET_FPRND" "@ @@ -5500,6 +5509,27 @@ (define_insn "round2" [(set_attr "type" "fp") (set_attr "fp_type" "fp_addsub_")]) +(define_insn "*xsrdpi2" + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=") + (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "")] + UNSPEC_XSRDPI))] + "TARGET__FPR && TARGET_VSX" + "xsrdpi %x0,%x1" + [(set_attr "type" "fp") + (set_attr "fp_type" "fp_addsub_")]) + +(define_expand "lrounddi2" + [(set (match_dup 2) + (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "")] + UNSPEC_XSRDPI)) + (set (match_operand:DI 0 "gpc_reg_operand" "") + (unspec:DI [(match_dup 2)] + UNSPEC_FCTID))] + "TARGET__FPR && TARGET_VSX" +{ + operands[2] = gen_reg_rtx (mode); +}) + ; An UNSPEC is used so we don't have to support SImode in FP registers. (define_insn "stfiwx" [(set (match_operand:SI 0 "memory_operand" "=Z")