From patchwork Tue Oct 6 13:24:44 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Fomin X-Patchwork-Id: 526762 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 99B50140D68 for ; Wed, 7 Oct 2015 00:25:21 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b=rbuAVOZw; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:message-id:references:mime-version :content-type:in-reply-to; q=dns; s=default; b=HVuapRsZ3ps9N1UPx kmE6vZ/IAbQR1m72+JmIAwb0dGALvuVyRjOH1Ym8Q9NGJn59sUkT1MMpk1lC+i5B xTFd3YgpcBF+09Ze53sIGCzcbt60FGFTjQj72kKkUhkEo6J4tOUzwzNIDIjOqCLt pIus5CJ45csJpNAPFMQiOcvek8= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:message-id:references:mime-version :content-type:in-reply-to; s=default; bh=m5WPru/h//Ya2adH1UxE9y1 8Rcc=; b=rbuAVOZw9AGfxGqPLpiB84SjqJTLM+lbLwx2bE4QJGguVzHq+almhEm DykYgfDqRTwFYyD20tzOHwMKC127i/eA/Q26osVf/FnAE1L0cdZuXlbSqIenyRA4 6emM4qMbJFpNV4HD+2ZE5XL54TZ4rH0iebIhuoL5Qqs0nbxfrsSM= Received: (qmail 75602 invoked by alias); 6 Oct 2015 13:25:14 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 75569 invoked by uid 89); 6 Oct 2015 13:25:11 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.6 required=5.0 tests=BAYES_00, FREEMAIL_FROM, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-wi0-f172.google.com Received: from mail-wi0-f172.google.com (HELO mail-wi0-f172.google.com) (209.85.212.172) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-GCM-SHA256 encrypted) ESMTPS; Tue, 06 Oct 2015 13:25:09 +0000 Received: by wiclk2 with SMTP id lk2so167008036wic.0 for ; Tue, 06 Oct 2015 06:25:07 -0700 (PDT) X-Received: by 10.194.48.102 with SMTP id k6mr41999359wjn.124.1444137906994; Tue, 06 Oct 2015 06:25:06 -0700 (PDT) Received: from msticlxl57.ims.intel.com (jfdmzpr02-ext.jf.intel.com. [134.134.137.71]) by smtp.gmail.com with ESMTPSA id r6sm5034284wia.0.2015.10.06.06.25.03 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 06 Oct 2015 06:25:05 -0700 (PDT) Date: Tue, 6 Oct 2015 16:24:44 +0300 From: Alexander Fomin To: Kirill Yukhin Cc: ubizjak@gmail.com, gcc-patches@gcc.gnu.org Subject: Re: [PATCH, i386, AVX512] PR target/67849: Avoid upper-bank registers when splitting vec_extract_lo instruction. Message-ID: <20151006132444.GA61168@msticlxl57.ims.intel.com> References: <20151005155446.GA55082@msticlxl57.ims.intel.com> <20151006122336.GE56984@msticlxl57.ims.intel.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20151006122336.GE56984@msticlxl57.ims.intel.com> User-Agent: Mutt/1.5.23 (2014-03-12) X-IsSubscribed: yes On Tue, Oct 06, 2015 at 03:23:39PM +0300, Kirill Yukhin wrote: > Hi, > On 05 Oct 18:01, Uros Bizjak wrote: > > On Mon, Oct 5, 2015 at 5:54 PM, Alexander Fomin > > wrote: > > > This patch addresses PR target/67849. Given a machine that does not > > > support AVX512VL, following "else" branch for vec_exract_lo insn > > > may result in a split using YMMs from upper-bank, hence invalid > > > assembly. Tuning define_insn pattern and define_split constraints > > > eliminates this problem. > > > > > > Please take a look at ChangeLog entries - not sure how to reference > > > to corresponding split in md. > > > > Just describe it as " splitter". There are some examples > > in ChangeLog. > W/ proper ChangeLog entry, change is OK for main trunk. > > -- > Thanks, K > > > > > Regards, > > > Alexander > > > --- Thanks, Uros. I've fixed ChangeLog entry for the splitter as well as operand predicate. Kirill, so could you check it in please? Regression testing is OK on x86_64-linux-gnu. Regards, Alexander --- gcc/ PR target/67849 * config/i386/sse.md (define_split vec_select/V8FI): Restrict split for upper-bank registers when target does not support AVX512VL. (define_insn "vec_extract_lo_"): Restrict split when target does not support AVX512VL. --- gcc/config/i386/sse.md | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 9b7a338..1f2b275 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -6924,7 +6924,8 @@ (parallel [(const_int 0) (const_int 1) (const_int 2) (const_int 3)])))] "TARGET_AVX512F && !(MEM_P (operands[0]) && MEM_P (operands[1])) - && reload_completed" + && reload_completed + && (TARGET_AVX512VL || (REG_P (operands[0]) && !EXT_REX_SSE_REG_P (operands[1])))" [(const_int 0)] { rtx op1 = operands[1]; @@ -6962,7 +6963,7 @@ (const_int 2) (const_int 3)])))] "TARGET_AVX512F && !(MEM_P (operands[0]) && MEM_P (operands[1]))" { - if () + if ( || !TARGET_AVX512VL) return "vextract64x4\t{$0x0, %1, %0|%0, %1, 0x0}"; else return "#";